CN-121985839-A - Power device and packaging method thereof

CN121985839ACN 121985839 ACN121985839 ACN 121985839ACN-121985839-A

Abstract

The application relates to the technical field of semiconductors and discloses a power device and a packaging method thereof. The power device disclosed by the application comprises a vertical conduction type power chip arranged on a pin metal frame with a boss structure and a plane conduction type chip arranged on an intermediate substrate with at least two layers of conductive paths, wherein signal contacts of the plane conduction type chip are connected with the signal contacts of the vertical conduction type power chip and the boss structure of the pin metal frame through copper wires of the bottom panel of the intermediate substrate, and the two chips form a stacked structure based on the intermediate substrate with the multiple layers of conductive paths, so that the thickness of the device is effectively reduced, the parasitic parameters of encapsulation are reduced, the electrical performance of the device is optimized, and meanwhile, the heat dissipation efficiency is improved. The application also discloses a packaging method for manufacturing the power device, which is used for manufacturing the power device with the advantages.

Inventors

HUANG CHANG
TANG QINGYUAN
DING LULU
Deng Zhijiong

Assignees

广东风华芯电科技股份有限公司

Dates

Publication Date: 20260505
Application Date: 20260227

Claims (10)

1. A power device is characterized by comprising a pin metal frame, an intermediate substrate with at least two layers of conductive paths, a vertical conduction type power chip Q1 and a plane conduction type chip Q2, wherein the pin metal frame, the intermediate substrate and the plane conduction type power chip Q2 are packaged together; The lead metal frame comprises a first mounting area and a second mounting area which are divided, wherein the bottom surfaces of the first mounting area and the second mounting area are positioned on the same horizontal plane, a device drain electrode pin is arranged on the bottom surface of the first mounting area and exposed out of a packaging body to form a drain electrode pin of a power device, the device drain electrode pin penetrates through the lead metal frame from the bottom surface of the first mounting area to the top surface of the first mounting area to form a drain electrode pad, at least one first boss is further arranged on the top surface of the first mounting area, the drain electrode of the vertical conduction type power chip Q1 is welded on the area, which is not arranged on the first boss, of the drain electrode pad through a conductive medium, a chip source electrode metal lug is arranged on the source electrode of the front surface of the vertical conduction type power chip Q1, a power device gate electrode metal lug is arranged on the grid electrode of the front surface of the vertical conduction type power chip Q1, and a power device source electrode pin are arranged on the bottom surface of the second mounting area, and the power device gate electrode pin and the power device source electrode pin are exposed out of the packaging body respectively, and form a gate electrode pin and a source electrode pin of the power device; The plane conduction type chip Q2 is welded on the chip mounting surface of the intermediate substrate, the drain electrode of the plane conduction type chip Q2 is connected with the drain electrode copper wire, the source electrode of the plane conduction type chip Q2 is connected with the source electrode copper wire, the grid electrode of the plane conduction type chip Q2 is connected with the grid electrode copper wire, the drain electrode copper wire is communicated with the drain electrode copper foil area up and down, the source electrode copper wire is communicated with the source electrode copper foil area up and down, and the grid electrode copper wire is communicated with the grid electrode copper foil area up and down; The intermediate substrate is arranged right above the first boss and the second boss of the lead metal frame, the chip source metal lug is connected with the drain copper foil region through a conductive adhesive, the chip gate metal lug is connected with the source copper foil region through a conductive adhesive, the device source metal lug is connected with the source copper foil region through a conductive adhesive, and the device gate metal lug is connected with the gate copper foil region through a conductive adhesive.
2. The power device of claim 1, wherein the second mounting region bottom surface is further provided with a Kelvin source pin, the Kelvin source pin is exposed out of the package body to form a Kelvin pin of the power device; The surface of the chip mounting surface of the intermediate substrate is provided with a Kelvin copper wiring, the bottom plate surface of the intermediate substrate is provided with a Kelvin copper foil area, the Kelvin copper wiring is communicated with the Kelvin copper foil area up and down, the Kelvin copper wiring is connected with a Kelvin electrode of a planar conduction type device Q2, and the Kelvin pin metal bump is connected with the Kelvin copper foil area through a conductive adhesive.
3. A power device is characterized by comprising a pin metal frame, an intermediate substrate with at least two layers of conductive paths, a vertical conduction type power chip Q1 and a plane conduction type chip Q2, wherein the pin metal frame, the intermediate substrate and the plane conduction type power chip Q2 are packaged together; The lead metal frame comprises a first mounting area, wherein the bottom surface of the first mounting area is provided with a device drain electrode pin, the device drain electrode pin is exposed out of a package body to form a drain electrode pin of a power device, the device drain electrode pin penetrates through the lead metal frame from the bottom surface of the first mounting area to the top surface of the first mounting area to form a drain electrode bonding pad, the top surface of the first mounting area is also provided with at least two first bosses, the drain electrode of the vertical conduction type power chip Q1 is welded on a region where the drain electrode bonding pad is not arranged on the first bosses through a conductive medium, a source electrode on the front surface of the vertical conduction type power chip Q1 is provided with a chip source electrode metal protruding block, and a grid electrode on the front surface of the vertical conduction type power chip Q1 is provided with a chip grid electrode metal protruding block, and the first bosses, the chip source electrode metal protruding blocks and the top surfaces of the chip grid electrode metal protruding blocks are positioned on the same plane; The plane conduction type chip Q2 is welded on the chip mounting surface of the intermediate substrate, the drain electrode of the plane conduction type chip Q2 is connected with the drain electrode copper wire, the source electrode of the plane conduction type chip Q2 is connected with the source electrode copper wire, the grid electrode of the plane conduction type chip Q2 is connected with the grid electrode copper wire, the drain electrode copper wire is communicated with the drain electrode copper foil area up and down, the source electrode copper wire is communicated with the source electrode copper foil area up and down, and the grid electrode copper wire is communicated with the grid electrode copper foil area up and down; The intermediate substrate is arranged right above the first boss of the lead metal frame, the chip source electrode metal lug is connected with the drain electrode copper foil region through a conductive adhesive, the chip gate electrode metal lug is connected with the source electrode copper foil region through a conductive adhesive, the intermediate substrate further comprises a device source electrode metal pin and a device gate electrode metal pin, a first end of the device source electrode metal pin is connected with the source electrode copper foil region through a conductive adhesive, a second end of the device source electrode metal pin extends out of the package body to form a source electrode pin of the power device, a first end of the device gate electrode metal pin is connected with the gate electrode copper foil region through a conductive adhesive, and a second end of the device gate electrode metal pin extends out of the package body to form a gate electrode pin of the power device.
4. The power device of claim 3, wherein the die mounting surface of the interposer substrate is provided with a Kelvin copper trace, the bottom surface of the interposer substrate is provided with a Kelvin copper foil area, the Kelvin copper trace is in up-down communication with the Kelvin copper foil area, the Kelvin copper trace is connected with a Kelvin electrode of the planar conductive device Q2, the power device further comprises a Kelvin source pin, a first end of the Kelvin source pin is connected with the Kelvin copper foil area through a conductive adhesive, and a second end of the Kelvin source pin extends out of the package to form the Kelvin pin of the power device.
5. The power device of claim 2 or 4, wherein the interposer substrate comprises three layers of copper wiring; The top-layer copper connecting wire comprises a first drain electrode copper wire and a second drain electrode copper wire which are matched with the drain electrode position of the plane conduction type chip Q2, a first source electrode copper wire and a second source electrode copper wire which are matched with the source electrode position of the plane conduction type chip Q2, a grid electrode copper wire which is matched with the grid electrode position of the plane conduction type chip Q2, and a Kelvin copper wire which is matched with the Kelvin electrode position of the plane conduction type chip Q2, wherein the grid electrode copper wire and the Kelvin copper wire are arranged in a straight line and then are parallel to the first drain electrode copper wire, the first source electrode copper wire, the second drain electrode copper wire and the second source electrode copper wire; The middle layer copper connecting wire is a preset drain copper foil area, a preset source copper foil area, a preset gate copper foil area and a preset Kelvin copper foil area which are arranged according to the drain area, the source area and the gate area of the plane conduction type chip Q2 and the device gate metal bump, the device source metal bump and the Kelvin pin metal bump of the lead metal frame; The bottom layer copper connecting wire extends from a preset drain copper foil area, a preset source copper foil area, a preset grid copper foil area and a preset Kelvin copper foil area of the middle copper connecting wire to the bottom plate surface of the middle substrate in the direction from the bottom plate surface of the middle substrate, and the bottom layer copper connecting wire forms the drain copper foil area, the source copper foil area, the grid copper foil area and the Kelvin copper foil area on the bottom plate surface of the middle substrate; The middle layer copper connecting wire is connected with the top layer copper connecting wire and the bottom layer copper connecting wire, and the area of the middle layer copper connecting wire is larger than the area of the mounting surface copper wiring and/or the area of the bottom plate copper foil area.
6. The power device of claim 5, wherein the gate copper trace and the kelvin copper trace are in a flat trace design, and a wire spacing between the gate copper trace and the kelvin copper trace is 50-500 μm.
7. The packaging method of the power device is characterized by comprising the following steps of: S100, preparing a lead metal frame, an intermediate substrate with at least two layers of conductive paths, M vertical conduction type power chips Q1 and M plane conduction type chips Q2, wherein the lead metal frame comprises N vertical conduction type power chip Q1 mounting positions, each vertical conduction type power chip Q1 mounting position comprises a first mounting area and a second mounting area which are divided, and the bottom surfaces of the first mounting area and the second mounting area are positioned on the same horizontal plane; the bottom surface of the first mounting area is provided with a device drain pin, the device drain pin penetrates through the lead metal frame from the bottom surface of the first mounting area to the top surface of the first mounting area to form a drain pad, the top surface of the first mounting area is also provided with at least one first boss, the bottom surface of the second mounting area is provided with a power device grid pin and a power device source pin, the top surface of the second mounting area is provided with at least one second boss, the top surfaces of the first boss and the second boss are positioned on the same plane, the intermediate substrate comprises a substrate surface and a chip mounting surface, and the intermediate substrate is provided with a plane conduction type chip Q2 mounting position corresponding to each vertical conduction type power chip Q2 mounting position, and drain copper wiring, source copper wiring and grid copper wiring are arranged on the chip mounting surface, and the substrate surface is provided with a drain copper foil area, a source copper foil area and a grid copper foil area; S200, a step of installing a vertical conduction type power chip Q1, in which a conductive bonding agent is coated on a drain electrode pad area of a lead metal frame, a drain electrode at the bottom of the vertical conduction type power chip Q1 is attached to the drain electrode pad and solidified to form firm electrical interconnection, a chip source electrode metal lug is manufactured on a source electrode of the vertical conduction type power chip Q1, a chip grid electrode metal lug is manufactured on a grid electrode, a device grid electrode metal lug is manufactured at a power device grid electrode pin position of the top surface of a second installation area, and a device source electrode metal lug is manufactured at a power device source electrode pin position; S300, mounting a planar conduction type chip Q2, namely coating conductive bonding agents on a drain copper wire, a source copper wire and a grid copper wire on a chip mounting surface of the intermediate substrate through a printing process, placing the planar conduction type chip Q2 in a corresponding position of the intermediate substrate in a flip-chip manner, and curing the intermediate substrate with confirmed alignment to form firm electrical interconnection; s400, placing the intermediate substrate and the plane conduction type chip Q2 component in a mold, injecting resin molding compound for curing, and forming a protective molding layer on one side of the intermediate substrate, on which the plane conduction type chip Q2 is mounted, so as to form a Q2 plastic sealing plate; S500, an assembling step, namely overturning a packaged Q2 plastic sealing plate, coating conductive bonding agents at positions corresponding to the positions where the metal bumps and the bosses of the vertical conduction type power chip Q1 are required to be welded, overturning and assembling a lead metal frame of the vertical conduction type power chip Q1, and carrying out up-down alignment combination through an alignment jig to enable the source metal bumps of the vertical conduction type power chip Q1 to be connected with a drain copper foil area, and the gate metal bumps of the vertical conduction type power chip Q1 to be connected with a source copper foil area on an intermediate substrate; S600, integrally molding and packaging, namely placing the whole assembly frame assembled in the step S500 in a mold, injecting high-temperature-resistant epoxy resin to wrap, packaging and solidifying to form a connecting piece packaging body, wherein the drain electrode pin, the grid electrode pin and the source electrode pin of the power device are exposed out of the packaging body, and respectively forming the drain electrode pin, the grid electrode pin and the source electrode pin of the power device; S700, cutting and slicing, namely cutting the connected package into single independent power devices by adopting a cutting process.
8. The packaging method of the power device is characterized by comprising the following steps of: S100, preparing a lead metal frame, an intermediate substrate with at least two layers of conductive paths, M vertical conduction type power chips Q1 and M plane conduction type chips Q2, wherein the lead metal frame comprises N vertical conduction type power chips Q1 mounting positions, each vertical conduction type power chip Q1 mounting position comprises a first mounting area, the bottom surface of the first mounting area is provided with a device drain electrode pin, the device drain electrode pin penetrates through the lead metal frame from the bottom surface of the first mounting area to the top surface of the first mounting area to form a drain electrode pad, the top surface of the first mounting area is also provided with at least two first bosses, the intermediate substrate comprises a bottom plate surface and a chip mounting surface, and each vertical conduction type power chip Q1 mounting position of the intermediate substrate corresponding to the lead metal frame is provided with a plane conduction type chip Q2 mounting position; S200, a step of installing a vertical conduction type power chip Q1, in which a conductive bonding agent is coated on a drain electrode pad area of a lead metal frame, a drain electrode at the bottom of the vertical conduction type power chip Q1 is attached to the drain electrode pad and solidified to form firm electrical interconnection; S300, mounting a planar conduction type chip Q2, namely coating conductive bonding agents on a drain copper wire, a source copper wire and a grid copper wire on a chip mounting surface of the intermediate substrate through a printing process, placing the planar conduction type chip Q2 in a corresponding position of the intermediate substrate in a flip-chip manner, and curing the intermediate substrate with confirmed alignment to form firm electrical interconnection; s400, placing the intermediate substrate and the plane conduction type chip Q2 component in a mold, injecting resin molding compound for curing, and forming a protective molding layer on one side of the intermediate substrate, on which the plane conduction type chip Q2 is mounted, so as to form a Q2 plastic sealing plate; S500, the packaging step is that a packaged Q2 plastic sealing plate is turned over, and conductive bonding agent is coated at a position corresponding to a position where a metal bump and a boss of a vertical conduction type power chip Q1 are required to be welded, a pin metal frame of the vertical conduction type power chip Q1 is turned over and assembled, and a positioning jig is used for up-down alignment combination, so that a source electrode metal bump of the vertical conduction type power chip Q1 is connected with a drain copper foil area, a gate electrode metal bump of the vertical conduction type power chip Q1 is connected with a source copper foil area on an intermediate substrate, a first end of a source electrode metal pin of a device is arranged to be connected with the source copper foil area through a conductive adhesive, and a first end of a gate electrode metal pin of the device is connected with the gate copper foil area through the conductive adhesive; S600, integrally molding and packaging, namely placing the whole assembly frame assembled in the step S500 in a mold, injecting high-temperature-resistant epoxy resin to wrap, packaging and solidifying, exposing the drain pin of the device outside the package to form a drain pin of the power device, and extending the second end of the source metal pin of the device and the second end of the gate metal pin of the device outside the package to form a source pin and a gate pin of the power device respectively; S700, cutting and slicing, namely cutting the connected package into single independent power devices by adopting a cutting process.
9. The method of claim 7, wherein the second mounting area is further provided with a kelvin source pin, the chip mounting surface of the interposer substrate is provided with a kelvin copper trace, the bottom plate surface of the interposer substrate is provided with a kelvin copper foil area, and the kelvin copper trace is in up-down communication with the kelvin copper foil area; in the step S200, a Kelvin pin metal bump with the top surface on the same plane with the device grid metal bump is prepared on the Kelvin source pin; in the step S500, a conductive bonding agent is coated on the kelvin lead metal bump, and the kelvin lead metal bump is connected with a kelvin copper foil area; In the step S600, the kelvin source pins are exposed outside the package to form kelvin pins of the power device.
10. The method of claim 7 or 8, further comprising, between the integrally molded packaging step and the dicing step, the steps of: Grinding and thinning, namely precisely grinding one side or two sides of the packaging body simultaneously; And (3) conducting pin tinning treatment, namely conducting tinning treatment on drain electrode pins, source electrode pins, grid electrode pins and welding areas of the power device.

Description

Power device and packaging method thereof Technical Field The application relates to the technical field of semiconductors, in particular to a power device formed by integrally packaging at least two chips and a packaging method thereof. Background With the development of power electronics technology to high frequency, high efficiency and high power density, wide bandgap semiconductor power devices (such as SiC JFET and GaN HEMT) are widely used due to their excellent material properties. In order to fully exert the performance advantages, transistors with different characteristics (such as normally-on JFET and normally-off HEMT) are often encapsulated in a single package with a common-source common-gate (cascoded) structure, which has the advantages of high performance and easy driving. However, the package structure of such a power device in the prior art relies on the conventional Wire Bonding (Wire Bonding) technology to realize the electrical interconnection between the chips and the external pins. As disclosed in the chinese patent publication No. CN109659302a, the present invention discloses a power module processing method and a power module, which have obvious limitations that, first, parasitic inductance and resistance introduced by a bonding wire are large, which severely restricts high-speed switching performance of a device, increases switching loss and voltage overshoot, and is contrary to high-frequency advantages of a wide bandgap semiconductor device. Secondly, the bonding wire arc height causes difficulty in further reduction of the packaging thickness, and miniaturization and thinning of products are hindered. In addition, the traditional packaging structure has a longer heat dissipation path, is not beneficial to control of the junction temperature of the chip, and affects the long-term working reliability and the power density improvement of the device. Disclosure of Invention Aiming at the problems of the structure of the existing power device formed by transistors with different characteristics, the embodiment of the application provides the power device and the packaging method thereof, which are used for solving the problems. The power device provided by the first embodiment of the application comprises a pin metal frame, an intermediate substrate with at least two layers of conductive paths, a vertical conduction type power chip Q1 and a plane conduction type chip Q2, wherein the pin metal frame, the intermediate substrate and the plane conduction type power chip Q2 are packaged together; The lead metal frame comprises a first mounting area and a second mounting area which are divided, wherein the bottom surfaces of the first mounting area and the second mounting area are positioned on the same horizontal plane, a device drain electrode pin is arranged on the bottom surface of the first mounting area and exposed out of a packaging body to form a drain electrode pin of a power device, the device drain electrode pin penetrates through the lead metal frame from the bottom surface of the first mounting area to the top surface of the first mounting area to form a drain electrode pad, at least one first boss is further arranged on the top surface of the first mounting area, the drain electrode of the vertical conduction type power chip Q1 is welded on the area, which is not arranged on the first boss, of the drain electrode pad through a conductive medium, a chip source electrode metal lug is arranged on the source electrode of the front surface of the vertical conduction type power chip Q1, a chip gate electrode metal lug is arranged on the grid electrode of the front surface of the vertical conduction type power chip Q1, and the grid electrode pin of the power device is arranged on the bottom surface of the second mounting area, and the grid electrode pin of the power device is exposed out of the packaging body, and the grid electrode pin of the power device is respectively formed on the top surface of the packaging body, and the top surface of the first metal lug is communicated with the second metal lug, and the top surface of the second metal lug is arranged on the top surface of the first lug and the second lug, and the second lug is communicated with the metal lug, and the top surface of the second lug is arranged on the top surface of the metal lug; The plane conduction type chip Q2 is welded on the chip mounting surface of the intermediate substrate, the drain electrode of the plane conduction type chip Q2 is connected with the drain electrode copper wire, the source electrode of the plane conduction type chip Q2 is connected with the source electrode copper wire, the grid electrode of the plane conduction type chip Q2 is connected with the grid electrode copper wire, the drain electrode copper wire is communicated with the drain electrode copper foil area up and down, the source electrode copper wire is communicated with the source electrode copper foil area up and down, and th