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CN-121985840-A - Power DFN framework, packaging body and preparation method

CN121985840ACN 121985840 ACN121985840 ACN 121985840ACN-121985840-A

Abstract

A Power DFN framework, a package and a preparation method relate to the technical field of semiconductors. The chip carrier comprises a first metal frame, a second metal frame and a metal clamping piece, wherein a flat chip carrying area is arranged on the top surface of the first metal frame, a plurality of integrally formed first side connecting ribs are arranged on the side portion of the first metal frame, a first half etching area is arranged on the bottom edge of the first metal frame, and a first pin is arranged at the end portion of the first metal frame. The second metal frame and the side part of the first metal frame are arranged at intervals, and the electric connection with the chip is realized through the metal clamping piece. The first and second side parts of the first and second metal frame side part integrated into one piece are connected with the rib, so that the overall structural strength of the frame can be enhanced, the frame is prevented from deforming in the production, carrying and packaging processes, the dimensional accuracy of the frame is ensured, a stable structural foundation is provided for the subsequent procedures of chip mounting, metal clip connection and the like, and the durability of the overall frame is improved. The pins at the end parts of the first metal frame and the second metal frame after encapsulation are exposed from the end surface of the encapsulation body respectively, so that tin plating is facilitated, and 100% of solder infiltration is realized.

Inventors

  • XIONG PENGCHENG
  • XU YACHAO
  • ZHOU DEXING
  • ZHAO ZHENZHONG
  • ZHU GUOWEI
  • CHEN RUNSHENG
  • WANG YI

Assignees

  • 扬州扬杰电子科技股份有限公司

Dates

Publication Date
20260505
Application Date
20260310

Claims (10)

  1. 1. A Power DFN framework, comprising: The chip comprises a first metal frame (100), wherein a flat chip bearing area is arranged on the top surface of the first metal frame, a plurality of integrally formed first side connecting ribs (110) are arranged on the side portions of the first metal frame, a first half etching area (120) is arranged on the bottom edge of the first metal frame, and first pins (130) are arranged at the end portions of the first metal frame (100).
  2. 2. The Power DFN framework of claim 1, wherein a first recess (131) is provided between the first pin (130) and the chip carrier region.
  3. 3. The Power DFN framework of claim 1, wherein the die carrying area of the top surface of the first metal frame (100) is provided with electrically connected dies (200).
  4. 4. A Power DFN framework according to claim 3, characterized in that the chip (200) is a schottky block recovery chip.
  5. 5. A Power DFN frame according to claim 1 or 3, characterized in that the side of the first metal frame (100) is provided with second metal frames (300) arranged at intervals; The second metal frame (300) is electrically connected with the chip (200) on the top surface of the first metal frame (100) through the metal clamping piece (400); the end part of the second metal frame (300) is provided with a second pin (330), and the top part of the second metal frame is provided with a metal sheet connecting area for connecting the metal clamping pieces (400).
  6. 6. The Power DFN frame according to claim 5, wherein the second metal frame (300) is provided with second outwardly extending side ribs (310) on the side.
  7. 7. The Power DFN framework of claim 5, wherein a second half-etched region (320) is provided at a bottom of the second metal frame (300).
  8. 8. The Power DFN framework of claim 5, wherein a second recess is provided between the second pin (330) and the sheet metal connection region.
  9. 9. A Power DFN package comprising a Power DFN frame according to claim 5, wherein the first metal frame (100) and the second metal frame (300) are encased by the package (500); The bottom surface of the first metal frame (100), the first side connecting ribs (110) and the first pins (130) are exposed from the package body respectively; The bottom surface of the second metal frame (300), the second side connecting ribs (310) and the second pins (330) are exposed from the package body respectively.
  10. 10. A method for preparing a Power DFN package, applied to preparing a Power DFN package according to claim 9, comprising the steps of: Starting a welding automatic line, precisely clamping a second metal frame (300) and a first metal frame (100) through an automatic clamping mechanism, and stably placing the second metal frame and the first metal frame on a designated station of a conveying track of the automatic line according to a preset positioning reference; step two, switching an automatic line to a dispensing station, and dispensing a proper amount of interconnection solder paste on the surface of a bonding pad of a first metal frame (100) at a position close to the center point of the bonding pad; Switching to an ejection station of the chip 200, selecting a vacuum suction nozzle matched with the chip 200, and sucking the ejected chip (200) to be attached to a preset glue point of the first metal frame (100); Step four, after the mounting is completed, the automatic line is switched to a chip dispensing station, and a proper amount of interconnection solder paste is dispensed on the surface of the mounted chip 200 and at a position close to the center point of the chip according to preset dispensing parameters; step five, switching to a dispensing station of the second metal frame (300), and dispensing a proper amount of interconnection solder paste at a designated position of the second metal frame (300) according to preset parameters; Step six, sucking and placing a metal clamping piece (400) at the central axis symmetry position of the surface of the chip (200) and stably placing the metal clamping piece at the central axis symmetry position of a chip welding window, ensuring the posture of the metal clamping piece (400) to be correct during mounting, and accurately attaching and realizing interconnection of a boss part and a metal area on the front surface of the chip; And seventhly, conveying the semi-finished product subjected to the assembly process into a vacuum reflow soldering furnace or a tunnel furnace through an automatic conveying mechanism, performing sintering treatment according to preset sintering process parameters, naturally cooling the semi-finished product to room temperature after the sintering is finished, and entering the subsequent process.

Description

Power DFN framework, packaging body and preparation method Technical Field The invention relates to the technical field of semiconductors, in particular to a Power DFN frame, a packaging body and a preparation method. Background The Power DFN diode is a Power diode product carrying Power DFN Power type pin-free flat package, the package is specially designed for optimizing a Power device, different from a common small-signal DFN package, common diode types comprise Schottky, fast recovery, ultra-fast recovery, TVS/ESD protection diodes, standard rectifier diodes and the like, and the Power diode is a main stream choice for Power related application in the fields of modern consumer electronics, automobile electronics, industry and communication by virtue of core advantages of small volume, high Power density, strong heat dissipation and high reliability. The Power DFN package adopts the design without the traditional pins, realizes welding by means of the bottom or side bonding pad, is provided with a large-area bare heat dissipation bonding pad, can be directly attached to a PCB, has extremely thin overall packaging thickness, is normally between 0.6 and 1.0mm, and has a part of small-size thickness as low as 0.4mm. Compared with traditional packaging such as SMA/SMB/SMC, SOT-223 and the like, the packaging area of the Power DFN diode can be saved by 50% -90%, the ultrathin structure is adapted to the design requirements of various ultrathin devices, meanwhile, the heat resistance of the large copper bottom heat dissipation pad is 30% -70% lower than that of the traditional packaging, the high total heat dissipation Power and the junction temperature of 175 ℃ can be supported, the small packaging can bear larger working current, for example, the DFN3820A specification can realize the current-voltage bearing capacity of 4A/600V, and the leadless structure also enables the device to have better vibration resistance and bending resistance. The diode has various mainstream packaging specifications, from a DFN1006 with the size of 1.0x0.6mm and the current less than or equal to 1A, which is suitable for consumer electronics, quick charge, 2.0x2.0mm and the current of 1-3A, to a DFN3333 with the current of 3.3x3.3mm and the current of 3-10A, which are commonly used in the fields of industry and automobile electronics, and a DFN3820A with the size of 3.8x2.0mm and the current of 2-4A, and a DFN5060 with the size of 5.0x6.0mm and the current of 5-20A in a high-power supply scene, and different specifications can be matched with different power and space requirements. The PowerDFN diodes of different types are respectively provided with an adaptation scene, the Schottky diode is mainly used for DC/DC conversion, fast charging and follow current links due to the characteristics of low forward voltage drop and high frequency, the fast recovery/ultra fast recovery diode is suitable for PFC and inverter circuits by virtue of high withstand voltage and short reverse recovery time, the TVS/ESD protection diode is mainly used for protecting interfaces and power supplies, and the standard rectifier diode can be used for general rectification to replace the traditional SMA/SMB packaging rectifier device. Power DFN (double flat leadless Package) has been widely used in devices such as Power diodes due to its small size, excellent heat dissipation, and excellent electrical properties. However, the metal frame structure adopted by the existing PowerDFN package still has the following technical drawbacks: 1. Insufficient package tightness and reliability The back edge of traditional metal frame is mostly level and smooth structure, and steam is easy to invade inside the encapsulation along the interface of frame and plastic envelope material, leads to the chip to wet, oxidation, and then causes device electrical property to descend even inefficacy, is difficult to satisfy the demand of high reliability application scene. 2. The welding reliability and the detection cost are higher The traditional pin structure is not beneficial to full image detection (AOI) of welding spots, and X-ray light detection with high cost has to be relied on in production, so that the production and manufacturing cost is high. 3. Poor stress management and structural stability Thermal stress generated by unmatched thermal expansion coefficients of the chip and the metal frame cannot be effectively released, and cracking of the chip or layering of the packaging body are easily caused. 4. Process compatibility and yield limitations The structural design of the existing frame is easy to cause uneven filling of plastic packaging materials, unsmooth air exhaust, air holes, hollows and the like in the plastic packaging process, and influences packaging yield and quality consistency. In summary, the conventional metal frame for Power DFN packaging has obvious disadvantages in terms of tightness, welding reliability, stress management, process compatibility, a