CN-121985842-A - Stacked substrate structure and manufacturing method thereof

Abstract

The invention discloses a stacked substrate structure and a manufacturing method thereof. The stacked substrate structure includes a first structure and a second structure. The first structure has a first engagement surface. The first structure includes a first circuit structure. The first circuit structure includes a plurality of first conductive layers and a first expansion modulation layer. The plurality of first conductive layers are stacked in a vertical direction. The first expansion modulation layer is arranged between the adjacent first conductive layers, wherein the thermal expansion coefficient of the first expansion modulation layer is larger than that of the first conductive layers. The second structure has a second engagement surface, wherein the second engagement surface of the second structure is disposed face-to-face with the first engagement surface of the first structure.

Inventors

• Qiu Weilan
• ZHANG XIANGHONG
• WU SHIXIAN
• HUANG YUWEI

Assignees

• 财团法人工业技术研究院

Dates

Publication Date

20260505

Application Date

20250103

Priority Date

20241030

Claims (20)

1. 1. A stacked substrate structure, comprising: a first structure having a first engagement surface, wherein the first structure comprises: A first circuit structure comprising: a plurality of first conductive layers stacked in a vertical direction, and A first expansion modulation layer disposed between adjacent first conductive layers, wherein the first expansion modulation layer has a thermal expansion coefficient greater than that of the first conductive layers, and A second structure having a second engagement surface, wherein the second engagement surface of the second structure is disposed face-to-face with the first engagement surface of the first structure.
2. 2. The stacked substrate structure of claim 1, wherein the plurality of first conductive layers comprises a first bond pad layer, the first bond pad layer being located on the first bonding surface, Wherein the second structure includes a second bond pad layer at the second bonding surface, the second bond pad layer in direct contact with the first bond pad layer.
3. 3. The stacked substrate structure of claim 2, wherein the material of the first and second bonding pad layers comprises nano-fine copper, nano-twin copper, or nano-fine-twin copper.
4. 4. The stacked substrate structure of claim 1, wherein the first line structure further comprises: A plurality of first via holes arranged between the adjacent first conductive layers, and The first conductive layers and the first via holes are arranged in the first insulating structure, wherein the material of the first insulating structure comprises polyimide, polybenzoxazole, benzocyclobutene or silicon oxide.
5. 5. The stacked substrate structure of claim 4, wherein the first expansion modulation layer is located in a portion of the plurality of first vias.
6. 6. The stacked substrate structure of claim 4, wherein the first expansion modulation layer is located between one of the plurality of first via holes and a corresponding one of the plurality of first conductive layers.
7. 7. The stacked substrate structure of claim 4, wherein a portion of the plurality of first vias comprises a metal-insulator-metal structure forming a capacitor.
8. 8. The stacked substrate structure of claim 2, wherein the second structure further comprises a second expansion modulation layer disposed on a side of the second bonding pad layer remote from the second bonding surface, the second expansion modulation layer having a coefficient of thermal expansion greater than a coefficient of thermal expansion of the second bonding pad layer, Wherein the first bond pad layer and the second bond pad layer are located between the first expansion modulation layer and the second expansion modulation layer.
9. 9. The stacked substrate structure of claim 4, wherein the first structure further comprises: The first chip is arranged on the first circuit structure and is electrically connected with the first circuit structure; the first molding body is arranged on the first circuit structure and encapsulates the first chip; A first conductive post disposed in the first molding body and electrically connected to the first circuit structure, and The top conducting layer is arranged on the first die sealing body and the first conducting column and is electrically connected with the first conducting column.
10. 10. The stacked substrate structure of claim 9, wherein the second structure comprises: A second molding body; the second circuit structure is arranged on the second die sealing body, wherein the second circuit structure comprises the second joint cushion layer; A third circuit structure arranged on one side of the second mold package opposite to the second circuit structure; a second conductive post arranged in the second molding body and electrically connected with the second circuit structure and the third circuit structure, The first chip is electrically connected with the third circuit structure through the first circuit structure, the second circuit structure and the second conductive post.
11. 11. The stacked substrate structure of claim 10, further comprising an inductor, the inductor comprising: a top wiring layer comprising a plurality of top wiring sections made up of portions of the top conductive layer; a bottom wiring layer including a plurality of bottom wiring sections made up of a portion of the third conductive layer of the third wiring structure; And a plurality of vertical connectors between the plurality of top line segments and the plurality of bottom line segments, wherein the plurality of vertical connectors include a portion of the first conductive pillars, a portion of the plurality of first via holes, a portion of the first bonding pad layer, a portion of the second bonding pad layer, and a portion of the second conductive pillars stacked in the vertical direction.
12. 12. A method of manufacturing a stacked substrate structure, comprising: Providing a first structure, wherein the first structure has a first engagement surface, the first structure comprising: A first circuit structure comprising: A plurality of first conductive layers stacked in a vertical direction, wherein the plurality of first conductive layers includes a first bonding pad layer located on the first bonding surface, and The first expansion modulation layer is arranged between the adjacent first conductive layers, and the thermal expansion coefficient of the first expansion modulation layer is larger than that of the first conductive layers; providing a second structure, wherein the second structure has a second bonding surface, the second structure comprises a second bonding pad layer positioned on the second bonding surface, and And bonding the first structure and the second structure through a hot-press bonding process, wherein the first bonding cushion layer is directly contacted with and connected with the second bonding cushion layer.
13. 13. The method of manufacturing a stacked substrate structure according to claim 12, wherein the first bonding pad layer of the first structure has a recess before bonding the first structure to the second structure, During the thermocompression bonding process, a distance Δd of a surface of the first bonding pad layer displaced in the vertical direction due to thermal expansion of the first expansion modulation layer is greater than or equal to a depth of the recess, so that the first bonding pad layer is in direct contact with the second bonding pad layer.
14. 14. The method of manufacturing a stacked substrate structure according to claim 13, wherein the distance Δd is represented by the following formula 1, [ 1] Δd=ΔT(d2×α 1 )+ΔT×d3(α 2 -α 1 ), In formula 1, Δd is the distance, Δt is the temperature difference before and after the thermocompression bonding process, d2 is the total thickness of the first bonding pad, the first expansion modulation layer, and the plurality of first conductive layers, d3 is the thickness of the first expansion modulation layer, α 1 is the thermal expansion coefficient of the first bonding pad, and α 2 is the thermal expansion coefficient of the first expansion modulation layer.
15. 15. The method of manufacturing a stacked substrate structure according to claim 13, wherein the distance Δd is 1 to 1000 times the depth of the recess.
16. 16. The method of manufacturing a stacked substrate structure of claim 13, wherein the forming of the first structure comprises: Forming a seed crystal layer on the carrier plate; forming the first bonding pad layer on the seed layer; Forming a first insulating layer on the first bonding pad layer, wherein the first insulating layer has a plurality of openings to expose a portion of the first bonding pad layer; forming the first expansion modulation layer in the plurality of openings; forming the first conductive layer over the first expansion modulation layer and the first insulating layer, and And stripping the carrier plate and removing the seed crystal layer to expose the first bonding cushion layer and the first insulating layer.
17. 17. The method of manufacturing a stacked substrate structure of claim 13, wherein the step of bonding the first structure to the second structure comprises: disposing the second bonding surface in face-to-face relation with the first bonding surface such that the first bonding pad layer is disposed in correspondence with the second bonding pad layer, the first insulating structure of the first bonding surface being in direct contact with the second insulating structure of the second bonding surface, and And performing the hot-press bonding process, wherein the first bonding cushion layer and the second bonding cushion layer are expanded by heating, so that the first bonding cushion layer and the second bonding cushion layer are in direct contact and are bonded metal to metal.
18. 18. The method of manufacturing a stacked substrate structure according to claim 17, wherein the first insulating structure is in direct contact with the second insulating structure after the thermocompression bonding process is performed.
19. 19. The method of manufacturing a stacked substrate structure according to claim 17, wherein the first insulating structure and the second insulating structure are spaced apart from each other after the thermocompression bonding process is performed.
20. 20. The method of claim 13, wherein the thermal compression bonding process is performed at a temperature of 250 ℃ or less.

Description

Stacked substrate structure and manufacturing method thereof Technical Field The present invention relates to a substrate structure and a method for manufacturing the same, and more particularly, to a stacked substrate structure and a method for manufacturing the same. Background With the demand of electronic products for multiple functions and fast instruction cycle, chip packages are gradually turned to three-dimensional (3D) stacking or 2.5-dimensional (2.5D) packaging development under the condition of limited two-dimensional (2D) space. In order to transmit more signals and maintain a high-speed and high-frequency transmission speed, it is necessary to increase the density of the wiring layout and shorten the transmission distance between chips as much as possible. However, the current packaging structure meeting the above requirements has complex process and poor yield. Disclosure of Invention The invention is directed to a stacked substrate structure and a manufacturing method thereof, which have simplified process and reduced manufacturing cost. According to an embodiment of the invention, the stacked substrate structure includes a first structure and a second structure. The first structure has a first engagement surface. The first structure includes a first circuit structure. The first circuit structure includes a plurality of first conductive layers and a first expansion modulation layer. The plurality of first conductive layers are stacked in a vertical direction. The first expansion modulation layer is arranged between the adjacent first conductive layers, wherein the thermal expansion coefficient of the first expansion modulation layer is larger than that of the first conductive layers. The second structure has a second engagement surface, wherein the second engagement surface of the second structure is disposed face-to-face with the first engagement surface of the first structure. According to an embodiment of the present invention, a method of manufacturing a stacked substrate structure includes the following steps. A first structure is provided, wherein the first structure has a first engagement surface. The first structure includes a plurality of first conductive layers and a first expansion modulation layer. The plurality of first conductive layers are stacked in a vertical direction. The first expansion modulation layer is arranged between the adjacent first conductive layers, wherein the thermal expansion coefficient of the first expansion modulation layer is larger than that of the first conductive layers. A second structure is provided, wherein the second structure has a second bonding surface, and the second structure includes a second bonding pad layer at the second bonding surface. The first structure is bonded to the second structure by a thermocompression bonding process, wherein the first bonding pad layer is in direct contact with and connected to the second bonding pad layer. Based on the above, the stacked substrate structure of the present invention is formed by bonding a plurality of stacked structures to each other, and by disposing the expansion modulation layer between the bonding pad and the wiring layer of the stacked structure, the bonding surface of the stacked structure can be directly bonded to another stacked structure, thereby simplifying the process and reducing the manufacturing cost. In addition, the direct connection of the plurality of stacked structures can shorten the distance of signal transmission and improve the signal transmission speed. Drawings FIG. 1 is a schematic cross-sectional view of a stacked substrate structure according to an embodiment of the present invention; FIGS. 2A-2E are schematic partial enlarged cross-sectional views of a stacked substrate structure according to an embodiment of the present invention; fig. 3A to 3C are schematic partial enlarged cross-sectional views of a stacked substrate structure according to an embodiment of the present invention; fig. 4A is a schematic partial perspective view of a stacked substrate structure according to an embodiment of the invention. FIG. 4B is a schematic top view of FIG. 4A; FIG. 5A is a schematic partial perspective view of a stacked substrate structure according to another embodiment of the present invention; FIG. 5B is a schematic top view of FIG. 5A; FIG. 6A is a schematic partial perspective view of a stacked substrate structure according to another embodiment of the present invention; FIG. 6B is a schematic top view of FIG. 6A; FIG. 7A is a schematic cross-sectional view of a stacked substrate structure according to an embodiment of the present invention; fig. 7B is a schematic partial perspective view of a stacked substrate structure according to an embodiment of the invention. Fig. 8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8I, 8J, 8K, 8L, 8M, 8N, 8O, 8P, 8Q, 8R' and 8S are schematic cross-sectional views of a manufacturing process of a stacked substrate structure according to an embodiment of