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CN-121985849-A - Packaging structure and method for inhibiting substrate warpage

CN121985849ACN 121985849 ACN121985849 ACN 121985849ACN-121985849-A

Abstract

The invention discloses a packaging structure and a method for inhibiting warpage of a substrate, wherein the packaging structure comprises the substrate, a solder mask layer is arranged on the surface of the substrate, a chip is covered on the surface of part of the solder mask layer and is electrically connected with the substrate through a welding structure penetrating through the solder mask layer, a polyimide film layer is arranged on the surface of the solder mask layer and is positioned on the periphery of the chip, and the thermal expansion coefficient of the polyimide film layer is smaller than that of the solder mask layer, so that the warpage direction of the substrate is matched with the warpage direction of the chip. Through setting up polyimide film layer on the solder mask layer surface to reduce the base plate warpage phenomenon, make the warpage direction of base plate and the warpage direction of chip tend to be unanimous, improve the bonding matching degree between chip and the base plate.

Inventors

  • HE YUPENG

Assignees

  • 渠梁电子有限公司

Dates

Publication Date
20260505
Application Date
20260409

Claims (7)

  1. 1. A package structure, comprising: the device comprises a substrate, wherein a solder mask layer is arranged on the surface of the substrate; the chip covers part of the surface of the solder mask layer and penetrates through the solder mask layer to be electrically connected with the substrate through a welding structure; The polyimide film layer is arranged on the surface of the solder mask layer and is positioned at the periphery of the chip; The thermal expansion coefficient of the polyimide film layer is smaller than that of the solder mask layer, so that the warping direction of the substrate is matched with that of the chip; The thickness of the polyimide film layer is 5-20um, the thermal expansion coefficient of the polyimide film layer is 15-30ppm/°c, and the thermal expansion coefficient of the solder mask layer is 80-130ppm/°c.
  2. 2. The package structure of claim 1, wherein a roughened interface structure is formed between the polyimide film layer and the solder resist layer by plasma etching, thereby enhancing interface bonding force between the two.
  3. 3. The package structure of claim 1, wherein the chip is electrically connected to the substrate by a plurality of solder balls.
  4. 4. A method of inhibiting warpage of a substrate, comprising the steps of: providing a substrate, wherein a chip and a solder mask layer are arranged on the surface of the substrate, and the chip is electrically connected with the substrate; coating polyimide precursor on the surface of the solder mask layer; drying and high-temperature imidizing and curing the polyimide precursor to form a polyimide film layer; the thermal expansion coefficient of the polyimide film layer is smaller than that of the solder mask layer, so that the warping of the solder mask layer is restrained in the reflow soldering temperature rising stage, and the surface layer compressive stress of the solder mask layer is reduced through elastic recovery in the cooling stage, so that the warping direction of the substrate is matched with the warping direction of the chip.
  5. 5. The method of claim 4, further comprising performing a plasma activation treatment on the surface of the solder mask layer before applying the polyimide precursor to the surface of the solder mask layer, thereby forming a micro-roughened structure.
  6. 6. The method of suppressing warpage of a substrate according to claim 5, wherein oxygen and argon are mixed to form an ion body, and the surface of the solder resist layer is subjected to etching treatment.
  7. 7. The method of claim 5, wherein the surface of the solder mask layer is plasma treated to form an activated group containing hydroxyl groups and carboxyl groups, and the activated group and the amino groups and carboxyl groups in the polyimide precursor form hydrogen bonding during curing, thereby improving the bonding strength between the polyimide film layer and the solder mask layer.

Description

Packaging structure and method for inhibiting substrate warpage Technical Field The invention relates to the technical field of packaging substrates, in particular to a packaging structure and a method for inhibiting substrate warpage. Background In the reflow soldering process of the package substrate, the package structure needs to undergo thermal cycle at a higher temperature, so that a warpage phenomenon is easily generated between the substrate and the chip. Because of the difference of thermal expansion coefficients between the inner material of the substrate and the surface solder mask layer, uneven thermal stress distribution is easy to occur on the surface layer of the substrate, so that the substrate has a cry-face warping shape with the middle part protruding upwards and the edge tilting downwards. The chip is usually made of silicon material, the thermal expansion coefficient is low, and the deformation generated in the temperature change process is different from that of the substrate, so that the warping directions of the chip and the substrate after reflow soldering are often inconsistent. When the warping direction of the chip and the substrate is opposite, the problem of poor local contact easily occurs in the chip mounting process, and part of the solder balls cannot be fully contacted with the corresponding bonding pads, so that the forming quality of the welding spots is affected, and even the bonding between the chip and the substrate is failed. Currently in the industry, to reduce substrate warpage, thermal expansion differences are typically reduced by adjusting the substrate material or optimizing the substrate internal layer structure, such as changing the thermal expansion coefficient of the substrate material or increasing the rigidity of the structural layer. However, such solutions often require redesigning the substrate material system, have long development cycles, and increase manufacturing costs, which have certain limitations in practical applications. Disclosure of Invention In order to overcome the defects, the invention aims to provide a packaging structure and a method for inhibiting the warpage of a substrate, and the polyimide film layer is arranged on the surface of the solder mask layer, so that the warpage phenomenon of the substrate is reduced, the warpage direction of the substrate and the warpage direction of a chip tend to be consistent, and the bonding matching degree between the chip and the substrate is improved. The invention discloses a packaging structure, which comprises: the device comprises a substrate, wherein a solder mask layer is arranged on the surface of the substrate; the chip covers part of the surface of the solder mask layer and penetrates through the solder mask layer to be electrically connected with the substrate through a welding structure; The polyimide film layer is arranged on the surface of the solder mask layer and positioned at the periphery of the chip welding area; The polyimide film layer has a thermal expansion coefficient smaller than that of the solder mask layer, so that the warping direction of the substrate is matched with that of the chip. Further, the thickness of the polyimide film layer is 5-20um, and the thermal expansion coefficient of the polyimide film layer is 15-30ppm/°c. Further, the thermal expansion coefficient of the solder mask layer is 80-130ppm/°c. Furthermore, a coarsened interface structure is formed between the polyimide film layer and the solder mask layer through plasma etching, so that the interface binding force of the polyimide film layer and the solder mask layer is enhanced. Further, the chip is electrically connected to the substrate through a plurality of solder balls. The invention also discloses a method for inhibiting the warpage of the substrate, which comprises the following steps: providing a substrate, wherein a chip and a solder mask layer are arranged on the surface of the substrate, and the chip is electrically connected with the substrate; coating polyimide precursor on the surface of the solder mask layer; drying and high-temperature imidizing and curing the polyimide precursor to form a polyimide film layer; the thermal expansion coefficient of the polyimide film layer is smaller than that of the solder mask layer, so that the warping of the solder mask layer is restrained in the reflow soldering temperature rising stage, and the surface layer compressive stress of the solder mask layer is reduced through elastic recovery in the cooling stage, so that the warping direction of the substrate is matched with the warping direction of the chip. Further, before the polyimide precursor is coated on the surface of the solder mask layer, plasma activation treatment is further performed on the surface of the solder mask layer, so that a micro-roughening structure is formed. Further, oxygen and argon are mixed to form an ion body, and the surface of the solder mask layer is subjected to etchin