CN-121985853-A - Three-dimensional integrated chip power management system, electronic equipment and method

CN121985853ACN 121985853 ACN121985853 ACN 121985853ACN-121985853-A

Abstract

The application relates to the technical field of integrated circuits, in particular to a three-dimensional integrated chip power management system, electronic equipment and a method, wherein the three-dimensional integrated chip power management system comprises a chip stacking body; the chip module comprises a side wall annular power supply bus, a plurality of tap distribution units and a plurality of tap distribution units, wherein the side wall annular power supply bus surrounds a side wall area of the chip stack body to form a closed annular conductor, and the tap distribution units are arranged on the side wall annular power supply bus and are used for electrically connecting a power supply network of each layer of chips in the chip stack body to the side wall annular power supply bus. Therefore, by constructing the closed annular power supply conductor on the side wall of the three-dimensional integrated chip stack body, connecting the closed annular power supply conductor with the packaging shell in parallel, integrating the decoupling capacitor and the sectional monitoring control, the problems of resistance voltage drop, transient inductance noise, electromagnetic interference, insufficient reliability of a power supply network and the like caused by the longitudinal power supply of the traditional TSV in the high-density 3D IC are solved, and the power supply integrity, the reliability and the system life of the three-dimensional integrated chip are improved.

Inventors

YAO PENG
ZHANG MENGYUN
GAO BIN
TANG JIANSHI
QIAN HE
WU HUAQIANG

Assignees

清华大学

Dates

Publication Date: 20260505
Application Date: 20260112

Claims (10)

1. A three-dimensional integrated chip power management system, comprising: A chip stack; A side wall annular power supply bus, which surrounds the side wall area of the chip stacking body to form a closed annular conductor; the plurality of tap distribution units are arranged on the side wall annular power supply bus and are used for electrically connecting a power supply network of each layer of chips in the chip stack body to the side wall annular power supply bus.
2. The system of claim 1, wherein the sidewall annular power bus bar comprises a sidewall power bus ring and a sidewall ground bus ring, wherein, The side wall power supply converging ring and the side wall ground converging ring are arranged in an up-down lamination mode, or the side wall power supply converging ring and the side wall ground converging ring are arranged in a concentric double-ring mode.
3. The system of claim 1, further comprising: and a plurality of bus ring control switches arranged in sequence along the annular conductor for dividing the annular conductor into a plurality of electrically isolated conductor segments.
4. A system according to claim 3, further comprising: at least one sensor array disposed corresponding to each electrically isolated conductor segment for acquiring current data, temperature data, and stress data corresponding to the conductor segment.
5. The system of claim 4, further comprising: the power management unit is respectively and electrically connected with the at least one sensor array and the plurality of bus ring control switches, and is used for determining the switching state of each bus ring control switch according to the current data, the temperature data and the stress data and controlling the corresponding bus ring control switch according to the switching state of each bus ring control switch.
6. The system of claim 5, further comprising: The bus ring carrier is coated on the outer sides of the chip stacking body, the side wall annular power supply bus and the power management unit to form an integrated packaging structure.
7. The system of claim 6, further comprising: The inner wall of the shell body is a metallization layer; The decoupling capacitor array is arranged between the shell body and the bus ring carrier.
8. An electronic device, characterized in that a three-dimensional integrated chip power management system according to any of claims 1-7 is implemented.
9. A three-dimensional integrated chip power management method, characterized in that a three-dimensional integrated chip power management system as claimed in any one of claims 1 to 7 is used, comprising the steps of: electrically connecting power supply nodes of chips of each layer in the chip stack to a ring conductor based on a plurality of tap distribution units; The chip stack is provided with a circumferential power supply via the annular conductor.
10. The method of claim 9, wherein, in electrically connecting the power supply nodes of the chips of each layer in the chip stack to the ring conductor, further comprising: Based on the sensor array, current data, temperature data, and stress data corresponding to the conductor segments are collected.

Description

Three-dimensional integrated chip power management system, electronic equipment and method Technical Field The present application relates to the field of integrated circuits, and in particular, to a three-dimensional integrated chip power management system, an electronic device, and a method. Background With the continuous rising of the demands of high-performance computing, artificial intelligence and other applications on chip computing power and energy efficiency, the three-dimensional integration technology has shown remarkable advantages in the aspects of improving integration density and shortening interconnection delay by vertically stacking a plurality of chip units. The concentration of power consumption and the complexity of power supply due to the chip stacking have increased dramatically, which has presented a serious challenge to the power supply integrity, and how to construct an efficient, stable and reliable power supply system for high-density 3D ICs (Three-DimensionalIntegratedCircuit, three-dimensional integrated circuits, through-silicon vias (Through-SiliconVia, vertical metal vias penetrating Through silicon wafer for achieving vertical interconnection of power, signals or thermal channels) has become a key bottleneck restricting the performance and reliability thereof. In the related art, solutions are mainly explored from both the wafer level and the package level. At the wafer level, the back side power supply network combines the nano through silicon vias and the embedded power supply rail, and introduces power from the back side of the chip, thereby effectively relieving the congestion of the front-end wiring layer and reducing the static IR voltage drop. At the package level, techniques such as through-mold vias, thick redistribution layers, fan-out packages, etc. are widely used to direct power from the outside of the package or the underlying substrate to the upper or periphery of the chip. In addition, the related art also embeds thin film decoupling capacitors in the package or carrier to suppress noise, and lateral interconnection between chips is achieved using sidewall metallization. However, the power supply path in the related art still depends on a longitudinal (Z-direction) through hole basically, current distribution is uneven, significant voltage drop is easy to generate in a region far away from the through hole, the limited cross-sectional area causes high current density and large local overheating risk, the reflow path also depends on a longitudinal structure, the formed large-area current loop can aggravate electromagnetic interference and weaken electrostatic discharge protection capability, high-frequency decoupling capability is insufficient, the traditional PDN (PowerDeliveryNetwork, power distribution network) has topological fixation from a package/external power supply to a power supply path system of each unit inside a chip, including TSV, RDL, package solder balls, board-level power supply network and the like, on-line monitoring and dynamic reconstruction capability is lacked, and when electromigration, stress cracking and other faults occur, the reliability and usability of the system face serious examination and need to be solved. Disclosure of Invention The application provides a three-dimensional integrated chip power management system, electronic equipment and a method, which are used for solving the problems of resistance voltage drop, transient inductance noise, electromagnetic interference, insufficient reliability of a power supply network and the like caused by longitudinal power supply of a traditional TSV in a high-density 3D IC. An embodiment of a first aspect of the present application provides a three-dimensional integrated chip power management system, including: A chip stack; A side wall annular power supply bus, which surrounds the side wall area of the chip stacking body to form a closed annular conductor; the plurality of tap distribution units are arranged on the side wall annular power supply bus and are used for electrically connecting a power supply network of each layer of chips in the chip stack body to the side wall annular power supply bus. Optionally, the side wall annular power supply bus comprises a side wall power supply bus ring and a side wall ground bus ring, wherein, The side wall power supply converging ring and the side wall ground converging ring are arranged in an up-down lamination mode, or the side wall power supply converging ring and the side wall ground converging ring are arranged in a concentric double-ring mode. Optionally, the method further comprises: and a plurality of bus ring control switches arranged in sequence along the annular conductor for dividing the annular conductor into a plurality of electrically isolated conductor segments. Optionally, the method further comprises: at least one sensor array disposed corresponding to each electrically isolated conductor segment for acquiring current data,