CN-121985863-A - Semiconductor package and method of forming the same

Abstract

The application provides a semiconductor package and a method of forming the same. The method includes providing a substrate, mounting a semiconductor die on a top surface of the substrate, forming a barrier wall on a peripheral region of the top surface of the semiconductor die, dispensing a first fluid material on the top surface of the semiconductor die, wherein the barrier wall prevents the first fluid material from flowing thereacross, and curing the first fluid material to form a backside metallization (BSM) layer.

Inventors

• JIN CHANGWU
• ZHENG ZHENXI
• CUI YONGZHU
• LI XIXIU

Assignees

• 星科金朋管理私人有限公司

Dates

Publication Date

20260505

Application Date

20241029

Claims (19)

1. 1. A method for forming a semiconductor package, the method comprising: Providing a substrate; Mounting a semiconductor die on a top surface of the substrate; Forming a barrier wall on a peripheral region of a top surface of the semiconductor die; Dispensing a first fluid material on a top surface of the semiconductor die, wherein the barrier wall prevents the first fluid material from flowing thereacross, and The first fluid material is cured to form a backside metallized BSM layer.
2. 2. The method of claim 1, wherein forming the barrier wall on the peripheral region of the top surface of the semiconductor die comprises: Dispensing a fluid composition on a top surface of the semiconductor die using an inkjet printing apparatus, an aerosol printing apparatus, an electrohydrodynamic EHD printing apparatus, a nozzle printing apparatus, or a spraying apparatus.
3. 3. The method of claim 1, wherein dispensing the first fluid material on a top surface of the semiconductor die comprises: The first fluid material is dispensed using an inkjet printing device, an aerosol printing device, an electrohydrodynamic EHD printing device, a nozzle printing device, or a spraying device.
4. 4. The method according to claim 1, wherein the method further comprises: dispensing a second fluid material over the BSM layer, wherein the barrier wall prevents the second fluid material from flowing thereacross, and The second fluid material is cured to form a barrier layer on the BSM layer.
5. 5. The method of claim 4, wherein dispensing the second fluid material on the BSM layer comprises: the second fluid material is dispensed using an inkjet printing device, an aerosol printing device, an electrohydrodynamic EHD printing device, a nozzle printing device, or a spraying device.
6. 6. The method of claim 4, wherein the BSM layer comprises silver, copper, gold, or aluminum, and the barrier layer comprises nickel, titanium, silicon oxide, aluminum oxide, graphene, boron nitride, or molybdenum sulfide.
7. 7. The method according to claim 1, wherein the method further comprises: an underfill encapsulant is formed between the semiconductor die and the substrate.
8. 8. The method according to claim 4, wherein the method further comprises: Providing a thermal interface material, TIM, layer having a bottom TIM surface and a top TIM surface; Attaching the bottom TIM surface to the barrier layer, and A heat spreader is attached to the top TIM surface.
9. 9. The method of claim 8, wherein the method further comprises: solder paste is formed on the bottom TIM surface and the top TIM surface, Wherein the bottom TIM surface is attached to the barrier layer via the solder on the bottom TIM surface and the heat spreader is attached to the top TIM surface via the solder on the top TIM surface.
10. 10. The method of claim 8, wherein the heat spreader comprises a cover and a surface finish layer attached to the cover, and the heat spreader is attached to the TIM layer via the surface finish layer.
11. 11. The method of claim 8, wherein the method further comprises: the TIM layer is reflowed to solder the TIM layer and the barrier layer together and to solder the TIM layer and the heat spreader together.
12. 12. The method of claim 8, wherein the TIM layer comprises indium or an indium silver alloy.
13. 13. A semiconductor package, characterized in that, the semiconductor package includes: A substrate; A semiconductor die mounted on a top surface of the substrate; A barrier wall formed on a peripheral region of a top surface of the semiconductor die, and A backside metallization (BSM) layer formed on a top surface of the semiconductor die, wherein the BSM layer is surrounded or partially surrounded by the barrier wall.
14. 14. The semiconductor package of claim 13, wherein the semiconductor package further comprises: a barrier layer formed on the BSM layer, wherein the barrier layer is surrounded or partially surrounded by the barrier wall.
15. 15. The semiconductor package of claim 14, wherein the BSM layer comprises silver, copper, gold, or aluminum, and the barrier layer comprises nickel, titanium, silicon oxide, aluminum oxide, graphene, boron nitride, or molybdenum sulfide.
16. 16. The semiconductor package of claim 13, wherein the semiconductor package further comprises: an underfill encapsulant formed between the semiconductor die and the substrate.
17. 17. The semiconductor package of claim 14, wherein the semiconductor package further comprises: a thermal interface material TIM layer disposed on the barrier layer, and A heat spreader disposed on the TIM layer.
18. 18. The semiconductor package of claim 17, wherein the heat spreader comprises a cover and a surface finish layer attached to the cover, and the heat spreader is attached to the TIM layer via the surface finish layer.
19. 19. The semiconductor package of claim 17, wherein the TIM layer comprises indium or an indium silver alloy.

Description

Semiconductor package and method of forming the same Technical Field The present disclosure relates generally to semiconductor technology, and more particularly, to a semiconductor package and method of forming the same. Background As consumers desire their electronic devices to be smaller, faster, and more capable, and to package more and more functionality into a single device, the semiconductor industry has been challenged with complex integration. Many electronic components in a device, such as microprocessors and integrated circuits, generate a significant amount of heat during operation. Overheating may reduce the performance, reliability, life expectancy of electronic components, and may even cause component failure. Heat sinks, and other heat dissipation solutions including Thermal Interface Materials (TIMs) are commonly used to dissipate heat and reduce the operating temperature of electronic components. However, the efficiency of existing heat dissipation methods may still be limited. Accordingly, there is a need for a semiconductor package having improved heat dissipation capabilities. Disclosure of Invention It is an object of the present application to provide a method for manufacturing a semiconductor package with improved heat dissipation capability. According to an aspect of the present application, a method for forming a semiconductor package is provided. The method may include providing a substrate, mounting a semiconductor die on a top surface of the substrate, forming a barrier wall on a peripheral region of the top surface of the semiconductor die, dispensing a first fluid material on the top surface of the semiconductor die, wherein the barrier wall prevents the first fluid material from flowing thereacross, and curing the first fluid material to form a backside metallization (BSM) layer. According to another aspect of the present application, a semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor die mounted on a top surface of the substrate, a barrier wall formed on a peripheral region of the top surface of the semiconductor die, and a backside metallization (BSM) layer formed on the top surface of the semiconductor die, wherein the BSM layer is surrounded or partially surrounded by the barrier wall. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. Furthermore, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. Drawings The accompanying drawings, which are incorporated in and form a part of this specification. The features shown in the drawings illustrate only some embodiments of the application and not all embodiments of the application unless the detailed description explicitly indicates otherwise, and the reader of this specification should not be inferred otherwise. Fig. 1 is a microscopic image showing a backside metallization (BSM) layer of a semiconductor package. Fig. 2A to 2H are top or cross-sectional views illustrating various steps of a method for forming a semiconductor package according to an embodiment of the present application. Fig. 3 is a cross-sectional view of a semiconductor package according to an embodiment of the present application. The same reference numbers will be used throughout the drawings to refer to the same or like parts. Detailed Description The following detailed description of exemplary embodiments of the application refers to the accompanying drawings, which form a part hereof. The drawings illustrate specific exemplary embodiments in which the application may be practiced. The detailed description, including the drawings, describes the embodiments in sufficient detail to enable those skilled in the art to practice the application. Those skilled in the art may further utilize other embodiments of the present application and with logic, mechanical, and other changes without departing from the spirit or scope of the application. The reader of the following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the appended claims. In the present application, the use of the singular includes the plural unless specifically stated otherwise. In the present application, the use of "or" means "and/or" unless stated otherwise. Furthermore, the use of the terms "include" and other forms of use, such as "comprise" and "contain," are not limiting. In addition, unless specifically stated otherwise, terms such as "element" or "component" encompass both elements and components comprising one unit as well as elements and components comprising more than one subunit. Furthermore, the section headings used herein are for organi