CN-121985864-A - Semiconductor packaging method and semiconductor packaging structure

CN121985864ACN 121985864 ACN121985864 ACN 121985864ACN-121985864-A

Abstract

The invention provides a semiconductor packaging method and a semiconductor packaging structure, wherein after a second semiconductor structure and a third semiconductor structure are bonded to a first semiconductor structure, an insulating layer is filled in a space between the second semiconductor structure and the third semiconductor structure, and the insulating layer has fluidity, so that a flat surface can be obtained when the insulating layer is formed, the problems of serious structure warpage and/or uneven stress distribution after bonding can be solved, and the quality and reliability of the semiconductor packaging structure are improved.

Inventors

SONG SHENGJIN
HU SHENG

Assignees

武汉新芯集成电路股份有限公司

Dates

Publication Date: 20260505
Application Date: 20241029

Claims (10)

1. A semiconductor packaging method, characterized in that the semiconductor packaging method comprises: providing a first semiconductor structure, a second semiconductor structure and a third semiconductor structure; bonding the second semiconductor structure and the third semiconductor structure to the first semiconductor structure with a spacing between adjacent second semiconductor structure and third semiconductor structure; Forming an insulating layer, wherein the insulating layer at least fills the space, and the insulating layer has fluidity; and curing the insulating layer.
2. The semiconductor packaging method of claim 1, wherein the first semiconductor structure has opposing first and second surfaces, the first surface being formed with a pad, the pad being surrounded by a dielectric layer, prior to bonding the second and third semiconductor structures to the first semiconductor structure, the second and third semiconductor structures being bonded to the second surface of the first semiconductor structure.
3. The semiconductor packaging method of claim 2, wherein the first semiconductor structure comprises a multi-layer wafer stack, and the second semiconductor structure and/or the third semiconductor structure comprises a multi-layer core particle stack, and the thickness of the second semiconductor structure and/or the third semiconductor structure is between 10 μm and 400 μm.
4. The semiconductor package method of claim 1, wherein the cured insulating layer has a first coefficient of thermal expansion, the second semiconductor structure has a second coefficient of thermal expansion, the third semiconductor structure has a third coefficient of thermal expansion, a difference between the first coefficient of thermal expansion and the second coefficient of thermal expansion, and a difference between the first coefficient of thermal expansion and the third coefficient of thermal expansion are less than or equal to 10% of a minimum of the first coefficient of thermal expansion, the second coefficient of thermal expansion, and the third coefficient of thermal expansion.
5. The method of claim 1, wherein the insulating layer comprises a suspension of a first material and a second material, the first material is a liquid, the second material is a solid, and a maximum particle diameter of the second material is less than or equal to 1/3 of a width of the gap.
6. The semiconductor packaging method according to claim 1, wherein after curing the insulating layer, the semiconductor packaging method further comprises: and grinding the cured insulating layer until the surface of the second semiconductor structure and/or the surface of the third semiconductor structure are exposed.
7. A semiconductor package structure is characterized by comprising a first semiconductor structure, a second semiconductor structure and a third semiconductor structure bonded to the first semiconductor structure with a space between adjacent second semiconductor structure and third semiconductor structure, and an insulating layer filling at least the space.
8. The semiconductor package method of claim 7, wherein the first semiconductor structure has opposing first and second surfaces, the first surface being formed with a pad, the pad being surrounded by a dielectric layer, the second and third semiconductor structures being bonded to the second surface of the first semiconductor structure.
9. The semiconductor packaging method of claim 8, wherein the first semiconductor structure comprises a multi-layer wafer stack, and the second semiconductor structure and/or the third semiconductor structure comprises a multi-layer core particle stack, and the thickness of the second semiconductor structure and/or the third semiconductor structure is between 10 μm and 400 μm.
10. The semiconductor package method of claim 7, wherein the insulating layer has a first coefficient of thermal expansion, the second semiconductor structure has a second coefficient of thermal expansion, the third semiconductor structure has a third coefficient of thermal expansion, a difference between the first coefficient of thermal expansion and the second coefficient of thermal expansion, and a difference between the first coefficient of thermal expansion and the third coefficient of thermal expansion are less than or equal to 10% of a minimum of the first coefficient of thermal expansion, the second coefficient of thermal expansion, and the third coefficient of thermal expansion.

Description

Semiconductor packaging method and semiconductor packaging structure Technical Field The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor packaging method and a semiconductor packaging structure. Background With the development of the integrated circuit industry entering the post-molar age, the key pitch and the size of the chip are continuously reduced, and accordingly, new integrated packaging modes, such as a solderless copper-copper bonding and Hybrid bonding (Hybrid bonding) technology, are developed, so that the integration density can be greatly improved. Hybrid bonding is a technique for simultaneously bonding metal electrodes and dielectric insulating layers on a wafer/chip. Micro bumps (μbump) are omitted so hybrid bonding can further reduce the interconnect pitch of the bond to below 10 μm. Thus, high density integration can be achieved using hybrid bonding techniques, which plays an irreplaceable role in 3D packaging. According to the object division of bonding, hybrid bonding may enable Wafer-to-Wafer bonding (W2W), die-to-Die bonding (D2D), and Die-to-Wafer bonding (Die-to-Wafer, D2W). For die-to-wafer bonding, the progress has also been made from single-layer die-to-wafer bonding to multi-layer die-to-wafer bonding to further improve the performance of the resulting semiconductor package. However, as the number of layers of core particles increases, the warpage and stress problems of the bonded wafer become more pronounced. Disclosure of Invention The invention aims to provide a semiconductor packaging method and a semiconductor packaging structure, which are used for solving the problems of serious wafer warpage and/or uneven stress distribution after bonding of core particles and wafers along with the increase of the number of core particle layers in the prior art. In order to solve the above technical problems, the present invention provides a semiconductor packaging method, including: providing a first semiconductor structure, a second semiconductor structure and a third semiconductor structure; bonding the second semiconductor structure and the third semiconductor structure to the first semiconductor structure with a spacing between adjacent second semiconductor structure and third semiconductor structure; Forming an insulating layer filling at least the space, the insulating layer having fluidity, and And curing the insulating layer. Optionally, in the semiconductor packaging method, the first semiconductor structure has a first surface and a second surface opposite to each other, a pad is formed on the first surface before the second semiconductor structure and the third semiconductor structure are bonded to the first semiconductor structure, the pad is wrapped by a dielectric layer, and the second semiconductor structure and the third semiconductor structure are bonded to the second surface of the first semiconductor structure. Optionally, in the semiconductor packaging method, the first semiconductor structure comprises a multi-layer wafer stack, the second semiconductor structure and/or the third semiconductor structure comprises a multi-layer core particle stack, and the thickness of the second semiconductor structure and/or the third semiconductor structure is 10-400 μm. Optionally, in the semiconductor packaging method, the cured insulating layer has a first thermal expansion coefficient, the second semiconductor structure has a second thermal expansion coefficient, the third semiconductor structure has a third thermal expansion coefficient, and a difference between the first thermal expansion coefficient and the second thermal expansion coefficient and a difference between the first thermal expansion coefficient and the third thermal expansion coefficient are less than or equal to 10% of a minimum value of the first thermal expansion coefficient, the second thermal expansion coefficient and the third thermal expansion coefficient. Optionally, in the semiconductor packaging method, in the forming an insulating layer, the insulating layer includes a suspension made of a first material and a second material, the first material is a liquid, the second material is a solid, and a maximum particle diameter of the second material is less than or equal to 1/3 of a width of the space. Optionally, in the semiconductor packaging method, after the insulating layer is cured, the semiconductor packaging method further includes: and grinding the cured insulating layer until the surface of the second semiconductor structure and/or the surface of the third semiconductor structure are exposed. The invention also provides a semiconductor packaging structure, which comprises a first semiconductor structure, a second semiconductor structure and a third semiconductor structure bonded to the first semiconductor structure, wherein a space is arranged between the second semiconductor structure and the third semiconductor structure, an