CN-121985865-A - Semiconductor packaging structure and preparation method thereof

CN121985865ACN 121985865 ACN121985865 ACN 121985865ACN-121985865-A

Abstract

The invention provides a semiconductor packaging structure and a preparation method thereof, wherein a diffusion barrier layer is formed on the upper surface of a first packaging chip, and the diffusion barrier layer is only ground in the process of grinding and thinning the first packaging layer, so that Cu metal columns and the first packaging chip are prevented from being ground simultaneously, cu metal residues on the first packaging chip can be prevented, and further the first packaging chip is prevented from being polluted by Cu metal diffusion, and thus the problems of reduced breakdown voltage, electric leakage and the like caused by functional failure of the Cu sensitive chip are avoided.

Inventors

MEI PENG
CAI QIFENG
WANG LING

Assignees

盛合晶微半导体(江阴)有限公司

Dates

Publication Date: 20260505
Application Date: 20241031

Claims (10)

1. A method of manufacturing a semiconductor package, the method comprising: providing a support substrate; Forming a first rewiring layer on the support substrate; forming a Cu metal column and a first packaging chip on the first rewiring layer, wherein the Cu metal column and the first packaging chip are respectively and electrically connected with the first rewiring layer, the first packaging chip is bonded on the first rewiring layer in a flip-chip mode, and the upper surface of the Cu metal column is higher than the upper surface of the first packaging chip; forming a diffusion barrier layer on the upper surface of the first packaged chip, wherein the plane size of the diffusion barrier layer is not larger than that of the first packaged chip; Forming a first packaging layer, wherein the first packaging layer coats the first rewiring layer, the Cu metal column, the diffusion barrier layer and the first packaging chip; Grinding and thinning the upper surface of the first packaging layer until the Cu metal column with the exposed surface flush with the upper surface of the first packaging layer and the diffusion barrier layer are formed; Sequentially forming a second rewiring layer and a second packaging chip on the first packaging layer, the Cu metal column and the diffusion barrier layer, wherein the second packaging chip is formed above the diffusion barrier layer, the lower surface of the second rewiring layer is electrically connected with the Cu metal column, and the upper surface of the second rewiring layer is electrically connected with the second packaging chip; Forming a second encapsulation layer, wherein the second encapsulation layer encapsulates the second rewiring layer, the second encapsulation chip, the first encapsulation layer and the first rewiring layer; removing the support substrate; and forming a metal bump on the lower surface of the first rewiring layer, wherein the metal bump is electrically connected with the first rewiring layer.
2. The method of manufacturing a semiconductor package according to claim 1, further comprising the step of forming a heat sink on an upper surface of the diffusion barrier layer before forming the second re-wiring layer, wherein a planar dimension of the heat sink is not greater than a planar dimension of the diffusion barrier layer, and the second package chip is formed on the upper surface of the heat sink.
3. The method of manufacturing a semiconductor package according to claim 2, wherein the heat spreader is formed by soldering the heat spreader to the diffusion barrier layer with a metal paste, the metal paste comprising one or a combination of silver paste and solder paste.
4. The method for manufacturing a semiconductor package according to claim 2, wherein the heat sink is a silicon block, the method for forming the heat sink is a thermal bonding method, or the heat sink is a Cu metal block, a Ni metal block, or a composite metal block, and the method for forming the heat sink is an electroplating method or a thermal bonding method.
5. The method of manufacturing a semiconductor package according to claim 1, wherein the diffusion barrier layer comprises a metal colloid, and the metal colloid comprises one or a combination of silver paste and solder paste.
6. The method of manufacturing a semiconductor package according to claim 5, wherein the diffusion barrier layer is formed by printing a predetermined dose of the metal colloid on the upper surface of the first package chip, and then curing the metal colloid.
7. The method of manufacturing a semiconductor package according to claim 1, wherein the diffusion barrier layer has a thickness of 20 μm to 40 μm.
8. The method of manufacturing a semiconductor package according to claim 1, wherein the diffusion barrier layer has a planar dimension equal to a planar dimension of the first package chip, and the heat spreader has a planar dimension equal to a planar dimension of the diffusion barrier layer.
9. The method of manufacturing a semiconductor package according to claim 1, further comprising the step of bonding a passive device under the first rewiring layer after forming the metal bump, the passive device being electrically connected to the first rewiring layer.
10. A semiconductor package structure characterized in that the semiconductor package structure is prepared by the method for preparing the semiconductor package structure according to any one of claims 1 to 9.

Description

Semiconductor packaging structure and preparation method thereof Technical Field The invention belongs to the technical field of semiconductor manufacturing, and relates to a semiconductor packaging structure and a preparation method thereof. Background The rapid development of electronic products is a main driving force for the evolution of the packaging technology nowadays, and miniaturization, high density, high frequency, high speed, high reliability and low cost are main stream development directions of advanced packaging. The existing consumer electronic product package generally adopts Package On Package (POP) stacked package, along with the increase of functional integration of the electronic product, the packaging structure is highly centralized, and heat generated in the working process of the chip can generate irreversible damage to the chip itself, so that the heat dissipation problem of the packaging structure needs to be considered, and the heat dissipation requirement of the product package is higher and higher. As shown in fig. 1 and 2, in the conventional package structure, a polishing method is generally adopted to expose the back surface of the chip 10 located at the lower layer to increase heat dissipation, and in the polishing process, for facilitating the subsequent electrical connection, the copper (Cu) metal pillars 20 on the periphery of the chip 10 are polished simultaneously to expose the surface of the Cu metal pillars 20 for the subsequent electrical connection, i.e. the composite interface of the Cu metal pillars 20/the chip 10/the package layer 30 is polished synchronously during polishing, and then the stacked package of the chip at the upper layer is performed. However, during the process of polishing the composite interface of the Cu metal post 20/the chip 10/the package layer 30, the Cu metal 40 remains on the back surface of the chip 10, and since the Cu metal has a relatively large diffusion coefficient, particularly Cu metal is very easily diffused in the chip material, the Cu metal 40 remains rapidly diffused into the chip 10 under the chip, which causes Cu contamination, and results in functional failure of the chip sensitive to Cu, such as breakdown voltage reduction, leakage, and the like. Disclosure of Invention In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor package structure and a method for manufacturing the same, which are used for solving the problem of Cu pollution of a chip caused by Cu metal diffusion in the prior art. To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor package structure, the method comprising: providing a support substrate; Forming a first rewiring layer on the support substrate; forming a Cu metal column and a first packaging chip on the first rewiring layer, wherein the Cu metal column and the first packaging chip are respectively and electrically connected with the first rewiring layer, the first packaging chip is bonded on the first rewiring layer in a flip-chip mode, and the upper surface of the Cu metal column is higher than the upper surface of the first packaging chip; forming a diffusion barrier layer on the upper surface of the first packaged chip, wherein the plane size of the diffusion barrier layer is not larger than that of the first packaged chip; Forming a first packaging layer, wherein the first packaging layer coats the first rewiring layer, the Cu metal column, the diffusion barrier layer and the first packaging chip; Grinding and thinning the upper surface of the first packaging layer until the Cu metal column with the exposed surface flush with the upper surface of the first packaging layer and the diffusion barrier layer are formed; Sequentially forming a second rewiring layer and a second packaging chip on the first packaging layer, the Cu metal column and the diffusion barrier layer, wherein the second packaging chip is formed above the diffusion barrier layer, the lower surface of the second rewiring layer is electrically connected with the Cu metal column, and the upper surface of the second rewiring layer is electrically connected with the second packaging chip; Forming a second encapsulation layer, wherein the second encapsulation layer encapsulates the second rewiring layer, the second encapsulation chip, the first encapsulation layer and the first rewiring layer; removing the support substrate; and forming a metal bump on the lower surface of the first rewiring layer, wherein the metal bump is electrically connected with the first rewiring layer. Optionally, before forming the second rewiring layer, a step of forming a heat dissipation block on the upper surface of the diffusion barrier layer is further included, wherein the plane size of the heat dissipation block is not larger than that of the diffusion barrier layer, and the second packaging chip is formed on the