CN-121985868-A - Wafer-level fan-out type packaging method and structure of radio frequency chip

CN121985868ACN 121985868 ACN121985868 ACN 121985868ACN-121985868-A

Abstract

The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a wafer-level fan-out type packaging method and structure of a radio frequency chip. The method comprises the steps of completing wafer reconstruction through temporary bonding, chip mounting and plastic packaging, manufacturing a copper column sacrificial layer on a bonding pad of a chip, leveling the surface of the chip through photoetching and grinding to form a cavity structure so as to improve radio frequency performance and eliminate steps formed between the chip and plastic packaging materials, forming a bonding pad leading-out structure through a dry film laying and rewiring process, and realizing back heat dissipation of the chip through a laser drilling and hole filling process. The invention improves the radio frequency performance through the cavity structure, improves the heat dissipation of the chip through laser drilling and hole filling processes, and provides a method for eliminating steps between the chip and the resin matrix.

Inventors

YE DONGDONG
GAO RAN
Ju Tingyi
LU JIAWEI
JI YONG

Assignees

中国电子科技集团公司第五十八研究所

Dates

Publication Date: 20260505
Application Date: 20260130

Claims (10)

1. A method for wafer level fan-out packaging of radio frequency chips, comprising: the reconstruction of the wafer is completed by means of temporary bonding, chip mounting and plastic packaging; Manufacturing a copper column sacrificial layer on a bonding pad of a chip; The surface of the chip is flattened through photoetching and grinding, so that a cavity structure is formed, the radio frequency performance is improved, and steps formed between the chip and the plastic package material are eliminated; forming a bonding pad leading-out structure through a dry film layout and rewiring process; and through laser drilling and hole filling processes, heat dissipation of the back surface of the chip is realized.
2. The method of claim 1, wherein the temporary bonding comprises attaching a temporary bonding film to a glass carrier or a metal carrier.
3. The method of claim 2, wherein the die attach and plastic packaging comprises attaching the diced individual die to a carrier by high precision die attach technology and plastic packaging with a resin material to form a plastic package.
4. The method of claim 3, wherein the performing wafer-level fan-out package further comprises separating the glass carrier or the metal carrier, and the temporary bonding film by a de-bonding technique to obtain a reconstructed wafer.
5. The wafer level fan-out package structure of claim 1, wherein fabricating the copper pillar sacrificial layer comprises performing the fabrication of the copper pillar sacrificial layer using photolithography, physical vapor deposition, and electroplating techniques.
6. The method of claim 1, wherein the planarizing the surface of the chip by photolithography and lapping comprises forming a first dielectric layer on the surface of the chip, forming a cavity by photolithography at a fixed location between each two adjacent copper pillar sacrificial layers, and planarizing the surface of the chip by lapping.
7. The method of claim 6, wherein the process of distributing dry films and re-wiring comprises the steps of distributing dry films on the first dielectric layer, manufacturing windows at fixed positions corresponding to the copper column sacrificial layer by using a photoetching technology, manufacturing a re-wiring layer by using photoetching, physical vapor deposition and electroplating technologies, realizing connection between the re-wiring layer and the copper column sacrificial layer, and realizing front bump manufacturing by using a wafer level grinding technology and a wafer level ball planting technology.
8. The method of claim 3, wherein the laser drilling and hole filling process comprises forming heat dissipation channels on the back surface of the plastic package material by laser drilling technology, and performing back surface hole filling by photolithography, physical vapor deposition and electroplating technology to form heat dissipation copper columns.
9. A wafer level fan-out package structure for a radio frequency chip, comprising: A plastic package material, wherein a chip is arranged in the plastic package material; The packaging structure comprises a plastic package material, a first dielectric layer, a copper column sacrificial layer, a second dielectric layer, a first dielectric layer, a second dielectric layer and a second dielectric layer, wherein the first dielectric layer is arranged on the front surface of the plastic package material; A dry film arranged between the first dielectric layer and the front rewiring layer; The heat dissipation copper columns are distributed in the back heat dissipation channel of the plastic package material at equal intervals.
10. The rf chip wafer level fan-out package of claim 9, further comprising front bumps, wherein a plurality of front bumps are formed on a surface of the front rewiring layer by ball placement.

Description

Wafer-level fan-out type packaging method and structure of radio frequency chip Technical Field The invention belongs to the technical field of integrated circuit packaging, and particularly relates to a wafer-level fan-out type packaging method and structure of a radio frequency chip. Background The design and manufacturing capabilities of rf microwave chips, particularly high-end chips, have become a key indicator for measuring the core competitiveness of enterprises in the high-tech field, and the importance of the rf microwave chips is self-evident. The microsystem technology is a key carrier and platform for enabling a radio frequency microwave chip to exert extreme performance, realizing miniaturization, multifunction and high reliability. The wafer-level fan-out type package can integrate chips with different functions, reduces the final package size and improves the performance of the microsystem component while achieving high integration level. Representative of the comparison are eWLB of infliximab, long electric ECP and station accumulation InFO. In order to meet the requirements of higher frequencies, higher power and higher efficiency, the requirements of heat dissipation capacity of packages are also increasing. The existing ceramic package generally adopts a co-firing process, has excellent heat dissipation performance, fills air or inert gas in a cavity, has the lowest dielectric constant, and can reduce parasitic capacitance of a bonding wire and a peripheral area of a chip to the greatest extent, so that the performance of a packaged circuit is closest to the performance of a bare chip tested on a probe station. The back of the chip of the existing wafer fan-out type packaging structure is made of plastic packaging material, the heat conductivity coefficient is low, a dielectric layer is arranged on the front of the chip, certain performance loss exists, meanwhile, a height difference exists between the chip and a resin matrix after the wafer is reconstructed, and the situation of open and short circuit possibly caused by photoresist breakage in the subsequent rewiring process can occur. Disclosure of Invention The invention aims to provide a wafer-level fan-out type packaging method and a structure thereof for a radio frequency chip, and the invention improves the radio frequency performance by forming a cavity structure at a fixed position; the method solves the step problem between the chip and the resin matrix after the wafer is reconstructed, improves the packaging yield, and simultaneously grows copper columns on the back surface of the chip to improve the heat dissipation capacity of the chip. In order to solve the above technical problems, the present invention provides a method for packaging a wafer level fan-out of a radio frequency chip, comprising: the reconstruction of the wafer is completed by means of temporary bonding, chip mounting and plastic packaging; Manufacturing a copper column sacrificial layer on a bonding pad of a chip; The surface of the chip is flattened through photoetching and grinding, so that a cavity structure is formed, the radio frequency performance is improved, and steps formed between the chip and the plastic package material are eliminated; forming a bonding pad leading-out structure through a dry film layout and rewiring process; and through laser drilling and hole filling processes, heat dissipation of the back surface of the chip is realized. Preferably, the temporary bonding comprises attaching a temporary bonding film on a glass carrier plate or a metal carrier plate. Preferably, the chip mounting and plastic packaging comprises the steps of mounting the diced single chip on a carrier plate through a high-precision chip mounting technology and adopting a resin material for plastic packaging so as to form a plastic packaging material. Preferably, the wafer reconstruction is completed by separating the glass carrier plate or the metal carrier plate and the temporary bonding film through a de-bonding technology so as to obtain a reconstructed wafer. Preferably, the manufacturing of the copper pillar sacrificial layer comprises the steps of manufacturing the copper pillar sacrificial layer by utilizing photoetching, physical vapor deposition and electroplating technology. Preferably, the flattening the surface of the chip by photoetching and grinding comprises the steps of forming a first dielectric layer on the surface of the chip, manufacturing a cavity at a fixed position between every two adjacent copper column sacrificial layers by utilizing a photoetching technology, and flattening the surface of the chip by a grinding technology. Preferably, the process for laying dry films and re-wiring comprises the steps of laying dry films on the first dielectric layer, manufacturing windows at fixed positions corresponding to the copper column sacrificial layer by utilizing a photoetching technology, manufacturing a re-wiring layer by utilizing photoetchi