CN-121985869-A - Semiconductor die package and method of manufacturing the same

Abstract

In the manufacturing method of the semiconductor die package, in the process of preparing an initial package substrate, a second insulating layer and a second metal layer are respectively stacked on two first conductive circuit layers, patterning treatment is carried out on the second metal layer at the lower layer to form a first shielding layer, the first shielding layer is positioned below the conductive bonding pad, and a second shielding layer is further formed at the bottom of the second groove, so that the second shielding layer, the first conductive block and the first shielding layer are electrically connected, the first shielding layer and the second shielding layer effectively surround the first semiconductor die, and further the first semiconductor die can be effectively prevented from being subjected to electromagnetic interference.

Inventors

• QIAN JIN
• XU FAZHEN
• Tian yanan

Assignees

• 日月新半导体(威海)有限公司

Dates

Publication Date

20260505

Application Date

20260408

Claims (10)

1. 1. A method for manufacturing a semiconductor die package is characterized by comprising the following steps: Providing a first core plate comprising a core plate body and conductive circuit layers covering upper and lower surfaces of the core plate body, and a first conductive block covering a middle region of the lower surface of the core plate body; A first insulating layer and a first metal layer are arranged on the upper surface and the lower surface of the first core plate in a laminated mode, patterning treatment is conducted on the two first metal layers, a first conductive circuit layer is formed respectively, a plurality of conductive bonding pads are formed on the first insulating layer on the lower surface of the first core plate, and the plurality of conductive bonding pads are arranged corresponding to the first conductive blocks; Then, a second insulating layer and a second metal layer are respectively laminated on the two first conductive circuit layers, patterning treatment is carried out on the two second metal layers, a second conductive circuit layer and a first shielding layer are formed, and the first shielding layer is positioned below the conductive bonding pad; Forming a plurality of conductive structures, wherein the conductive structures are electrically connected with the first shielding layer and the first conductive block to form an initial packaging substrate; Carrying out open pore treatment on the initial packaging substrate to form a first groove, wherein the first groove exposes the conductive pad, and a part of the first conductive block is removed in the process of forming the first groove; providing a first semiconductor die in the first groove, wherein the first semiconductor die is electrically connected with the conductive pad, and a first packaging layer covering the first semiconductor die is formed in the first groove; forming a second groove, and forming a plurality of through holes exposing the first conductive blocks at the bottom of the second groove; forming a second shielding layer at the bottom of the second groove, so that the second shielding layer, the first conductive block and the first shielding layer are electrically connected; A second encapsulation layer is then formed to fill the second recess.
2. 2. The method of manufacturing a package of a semiconductor die of claim 1, wherein a first conductive via is formed in the core body, the first conductive via electrically connecting the conductive trace layers of the upper and lower surfaces of the core body.
3. 3. The method of manufacturing a package of a semiconductor die of claim 1, wherein a via is formed in the first insulating layer before the first metal layer is disposed on the upper and lower surfaces of the first core plate, and further wherein a second conductive via is formed in the first insulating layer during the formation of the first metal layer.
4. 4. The method of manufacturing a package of a semiconductor die as recited in claim 1, wherein a pad protective layer is formed over the conductive pads before the second insulating layer and the second metal layer are laminated over the two first conductive trace layers, respectively.
5. 5. The method of manufacturing a package of semiconductor die as recited in claim 1, further comprising forming a second semiconductor die on the second conductive trace layer, and then forming a third encapsulation layer, the third encapsulation layer encapsulating the second semiconductor die.
6. 6. The method of manufacturing a package of semiconductor die as recited in claim 5, wherein a third semiconductor die is disposed on the second encapsulation layer, and a fourth encapsulation layer is formed on the third semiconductor die such that an upper surface of the fourth encapsulation layer is flush with an upper surface of the second insulating layer of an upper layer.
7. 7. The method of manufacturing a package of a semiconductor die as recited in claim 6, wherein a third conductive trace layer is formed on an upper surface of the fourth package layer and an upper surface of the second insulating layer on the upper layer such that the third conductive trace layer is electrically connected to the third semiconductor die.
8. 8. The method of manufacturing a package of semiconductor dies of claim 7, wherein a fourth semiconductor die is formed on the third conductive trace layer while a second semiconductor die is formed on the second conductive trace layer.
9. 9. The method of manufacturing a package of a semiconductor die of claim 1, wherein a passivation protection layer is formed over the first shielding layer.
10. 10. A semiconductor die package characterized in that the semiconductor die package is formed by the method of any one of claims 1-9.

Description

Semiconductor die package and method of manufacturing the same Technical Field The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor die package and a method of manufacturing the same. Background Semiconductor packaging is a key element in integrated circuit fabrication, and is a core technology for electrically connecting a chip to an external circuit, mechanically supporting the chip, and protecting the environment. The chip not only provides physical protection for the precise fragile chip and prevents damage of external moisture, dust and mechanical impact, but also realizes efficient signal transmission and power supply of the chip and a Printed Circuit Board (PCB) through structures such as metal pins, solder balls or bumps and the like. With the evolution of semiconductor technology to high density, high performance and low power consumption, packaging technology has been developed from traditional pin-type packaging (such as DIP) to advanced forms such as Ball Grid Array (BGA), chip Scale Packaging (CSP), system In Package (SiP) and 3D packaging, which plays an irreplaceable role in improving integration level, reducing volume, optimizing heat dissipation and reducing signal delay, and becomes an important support for promoting miniaturization, intellectualization and multifunctionalization of electronic devices. Along with the miniaturization of semiconductor packages, how to optimize the manufacturing process of the semiconductor packages and further improve the electromagnetic shielding performance of the semiconductor packages has attracted attention in the industry. Disclosure of Invention It is an object of the present invention to overcome the deficiencies of the prior art described above and to provide a semiconductor die package and method of manufacturing the same. To achieve the above object, the present invention provides a method for manufacturing a package of a semiconductor die, comprising the steps of: a first core plate is provided, the first core plate comprising a core plate body and conductive line layers covering upper and lower surfaces of the core plate body, and a first conductive block covering a middle region of the lower surface of the core plate body. And a first insulating layer and a first metal layer are respectively arranged on the upper surface and the lower surface of the first core plate in a lamination mode, patterning treatment is carried out on the two first metal layers to form first conductive circuit layers respectively, a plurality of conductive bonding pads are formed on the first insulating layer on the lower surface of the first core plate, and the conductive bonding pads and the first conductive blocks are correspondingly arranged. And then, respectively laminating a second insulating layer and a second metal layer on the two first conductive circuit layers, and carrying out patterning treatment on the two second metal layers to form a second conductive circuit layer and a first shielding layer, wherein the first shielding layer is positioned below the conductive bonding pad. And forming a plurality of conductive structures, wherein the plurality of conductive structures are electrically connected with the first shielding layer and the first conductive block to form an initial packaging substrate. And carrying out opening treatment on the initial packaging substrate to form a first groove, wherein the first groove exposes the conductive pad, and a part of the first conductive block is removed in the process of forming the first groove. And arranging a first semiconductor die in the first groove, wherein the first semiconductor die is electrically connected with the conductive bonding pad, and a first packaging layer covering the first semiconductor die is formed in the first groove. And forming a second groove, and forming a plurality of through holes exposing the first conductive blocks at the bottom of the second groove. And forming a second shielding layer at the bottom of the second groove, so that the second shielding layer, the first conductive block and the first shielding layer are electrically connected. A second encapsulation layer is then formed to fill the second recess. As a preferred embodiment, first conductive through holes are formed in the core plate body, the first conductive through holes electrically connecting the conductive line layers of the upper and lower surfaces of the core plate body. As a preferred embodiment, a via hole is formed in the first insulating layer before the first metal layer is provided on the upper and lower surfaces of the first core board, and further, a second conductive via hole is formed in the first insulating layer in the process of forming the first metal layer. As a preferred embodiment, a pad protection layer covering the conductive pads is formed before the second insulating layer and the second metal layer are respectively laminated on the two