CN-121985870-A - Electronic device

Abstract

The present disclosure provides an electronic device. The electronic device comprises a base part, a circuit structure, an insulating structure, a first conductive layer, a through hole structure, a first outer layer and a second outer layer. The circuit structure is disposed on a first surface of the base portion. The insulating structure is disposed on the circuit structure. The first conductive layer is disposed on the insulating structure. The through hole structure extends through the insulating structure and is electrically connected with the first conductive layer and the circuit structure. The first outer layer is disposed on the first conductive layer. The second outer layer is disposed on the first outer layer. The second outer layer includes an oxide material to improve a co-planarity of an outermost surface of the second outer layer.

Inventors

• FANG WEIQUAN

Assignees

• 南亚科技股份有限公司

Dates

Publication Date

20260505

Application Date

20250403

Priority Date

20241029

Claims (20)

1. 1. An electronic device, comprising: a base portion having a first surface; a circuit structure disposed on the first surface of the base portion; An insulating structure disposed on the circuit structure; A first conductive layer disposed on the insulating structure; A through hole structure extending through the insulating structure and electrically connected to the first conductive layer and the circuit structure; A first outer layer disposed on the first conductive layer, and A second outer layer disposed on the first outer layer, wherein the second outer layer comprises an oxide material to improve a co-planarity of an outermost surface of the second outer layer.
2. 2. The electronic device of claim 1, wherein the base portion comprises silicon.
3. 3. The electronic device of claim 1, wherein the first surface of the base portion is an active surface.
4. 4. The electronic device of claim 1, wherein the circuit structure is a redistribution layer structure and comprises a plurality of dielectric layers and a plurality of redistribution layers embedded in the plurality of dielectric layers.
5. 5. The electronic device of claim 1, further comprising: A first intermediate layer disposed between the first surface of the base portion and the circuit structure for electrically insulating the circuit structure from the first surface of the base portion, and The first interconnecting holes are arranged in the first intermediate layer and are used for electrically connecting the circuit structure and the first surface of the base part.
6. 6. The electronic device of claim 1, further comprising: and the second conductive layer is arranged between the circuit structure and the insulating structure, and the through hole structure contacts the second conductive layer.
7. 7. The electronic device of claim 6, further comprising: A second intermediate layer disposed between the circuit structure and the second conductive layer for electrically insulating the circuit structure from the second conductive layer, and The second interconnecting holes are arranged in the second intermediate layer and are used for electrically connecting the circuit structure and the second conductive layer.
8. 8. The electronic device of claim 1, wherein the insulating structure comprises: a first insulating layer disposed on the circuit structure; a second insulating layer disposed on the first insulating layer, and And a third insulating layer disposed on the second insulating layer, wherein the via structure extends through the first insulating layer, the second insulating layer and the third insulating layer.
9. 9. The electronic device of claim 8, wherein the thickness of the third insulating layer is greater than the thickness of the second insulating layer and a thickness of the first insulating layer.
10. 10. The electronic device of claim 8, wherein a material of the third insulating layer is the same as a material of the first insulating layer, and the material of the third insulating layer is different from a material of the second insulating layer.
11. 11. The electronic device of claim 1, wherein the insulating structure defines a via extending through the insulating structure, and the via structure includes an interconnect layer disposed on sidewalls of the via.
12. 12. The electronic device of claim 11, wherein the interconnect layer and the first conductive layer are formed simultaneously and integrally.
13. 13. The electronic device of claim 11, wherein the first outer layer comprises a first extension disposed on the interconnect layer and extending into the via.
14. 14. The electronic device of claim 13, wherein the second outer layer includes a second extension disposed on the first extension of the first outer layer and extending into the through hole.
15. 15. The electronic device of claim 1, wherein the second outer layer defines a closed void.
16. 16. The electronic device of claim 15, wherein the closed void horizontally overlaps the first outer layer.
17. 17. The electronic device of claim 15, wherein the enclosed void horizontally overlaps the first conductive layer.
18. 18. The electronic device of claim 15, wherein the enclosed void horizontally overlaps the insulating structure.
19. 19. The electronic device of claim 15, wherein the closed void horizontally overlaps the via structure.
20. 20. The electronic device of claim 1, further comprising: A bump disposed on the second outer layer and electrically connected to the first conductive layer; A main portion extending through the first and second outer layers and contacting the first conductive layer, and An extension portion disposed on a first surface of the second outer layer.

Description

Electronic device Technical Field The priority of U.S. patent application Ser. No. 18/929,989 (i.e., priority date "10/29 of 2024"), the contents of which are incorporated herein by reference in their entirety, is claimed. The present disclosure relates to an electronic device, an assembly structure, and a manufacturing method, and more particularly, to an electronic device including an outermost layer having an oxide material, an assembly structure including the electronic device, and a manufacturing method. Background Semiconductor structures are used in a variety of electronic applications, and the dimensions of semiconductor structures are continually shrinking to meet current application requirements. However, various problems occur during the shrinking process, affecting the final electrical characteristics, quality, cost and yield. A typical semiconductor structure is provided with a plurality of bumps on its outer surface. If the outer surface is a wavy surface, the bumps will be inclined or have different heights. Therefore, a poor connection will be formed between the semiconductor structure and another electronic device, and the yield of the assembled structure will be reduced. Thus, the coplanarity and planarity of the outer surfaces of semiconductor structures is a critical issue. The background discussion section provides background information only. Statements in the background discussion do not constitute an admission that the subject matter disclosed herein constitutes prior art with respect to the present disclosure, and any portion of the background discussion is not used as an admission that any portion of the present disclosure constitutes prior art with respect to the present disclosure. The above description of "prior art" merely provides background art, and it is not admitted that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as any part of the present disclosure. Disclosure of Invention The present invention is directed to an electronic device, which solves at least one of the above problems. An embodiment of the present disclosure provides an electronic device. The electronic device comprises a base part, a circuit structure, an insulating structure, a first conductive layer, a through hole structure, a first outer layer and a second outer layer. The base portion has a first surface. The circuit structure is disposed on the first surface of the base portion. The insulating structure is disposed on the circuit structure. The first conductive layer is disposed on the insulating structure. The through hole structure extends through the insulating structure and is electrically connected with the first conductive layer and the circuit structure. The first outer layer is disposed on the first conductive layer. The second outer layer is disposed on the first outer layer. The second outer layer includes an oxide material to improve the co-planarity of an outermost surface of the second outer layer. Another embodiment of the present disclosure provides an assembled structure. The assembly structure comprises a first electronic device, a second electronic device and a substrate. The first electronic device comprises a base part, an outermost layer and a bump. The base portion has a first surface. The outermost layer is disposed adjacent the first surface of the base portion. The outermost layer includes an oxide material to improve a co-planarity of an outermost surface of the outermost layer. The bump extends through the outermost layer and beyond the outermost surface of the outermost layer. The second electronic device comprises a base part, a through hole, a welding pad and a connecting element. The base portion has a first surface and a second surface opposite the first surface. The through hole extends through the base portion. The welding pad is arranged near the second surface of the base part of the second electronic device and is electrically connected with the through hole and the bump of the first electronic device. The connecting element is arranged near the first surface of the base part of the second electronic device and is electrically connected to the welding pad through the through hole. The substrate is electrically connected to the connecting element. Another embodiment of the present disclosure provides a method of manufacturing an electronic device. The method includes providing a body including a base portion having a first surface, a circuit structure disposed on the first surface of the base portion, and an insulating structure disposed on the circuit structure, forming a via extending through the insulating structure, forming a first conductive layer on the insulating structure and forming an interconnect layer on a sidewall of the via, wherein the first conductive layer is connected to the interconnect