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CN-121985872-A - Pre-packaged panel-level package

CN121985872ACN 121985872 ACN121985872 ACN 121985872ACN-121985872-A

Abstract

The invention discloses a pre-packaged panel-level package, and belongs to the field of semiconductor packaging. The method comprises the steps of firstly welding a wafer with a circuit board substrate with a via hole to form pre-packaging monomers, then fixing a plurality of pre-packaging monomers on a wafer carrier plate in an array mode of downwards packaging bonding pads, then carrying out integral epoxy resin plastic packaging and curing, optionally carrying out top surface grinding to expose the back surface of the wafer and coating a high heat conduction layer, and finally stripping and cutting the carrier plate to obtain independent packaging monomers. The invention advances the high-precision interconnection step to the single manufacturing stage through the pre-integration strategy, simplifies the panel-level packaging process, improves the production yield and flexibility, and is convenient for integrating an efficient heat dissipation scheme. The structure is compact and reliable, and is suitable for advanced packaging of multiple chips and high heat dissipation requirements.

Inventors

  • ZHAO ZHENTAO

Assignees

  • 赵振涛

Dates

Publication Date
20260505
Application Date
20251215

Claims (3)

  1. 1. A pre-packaged panel-level package is characterized by comprising a wafer, a circuit board substrate, a wafer carrier plate, a temporary bonding layer, an epoxy resin packaging layer, and a packaging layer, wherein bonding pads are arranged on the bottom surface of the wafer, the circuit board substrate consists of a top circuit layer, an insulating board core layer and a bottom circuit layer, the substrate top layer bonding pads corresponding to the bonding pads on the bottom surface of the wafer are arranged on the top circuit layer, the packaging pads and the substrate top layer bonding pads are respectively corresponding to each other and are connected through holes of the insulating board core layer, the wafer is welded on the substrate top layer bonding pads through the bottom surface bonding pads and is integrally welded with the circuit board substrate to form pre-packaged monomers, the bonding pads on the bottom surface of the wafer are connected with the packaging bonding pads arranged on the bottom circuit board substrate through the top circuit layer and through holes of the insulating board core layer, two or more than two wafers are firstly prepared into one group of pre-packaged monomers, the wafer carrier plate is coated on the top surface of the wafer carrier plate, the temporary bonding layer is coated on the packaging pads are respectively corresponding to the packaging pads, the packaging pads are arranged on the top surface of the wafer carrier plate according to set position coordinates, the temporary bonding layer is coated on the wafer carrier plate, and the whole packaging layer is cut and the whole packaging layer is glued to obtain the whole packaging sheet after the packaging sheet is cut and the whole packaging sheet is subjected to the whole packaging.
  2. 2. The pre-packaged panel-level package of claim 1, wherein after the whole epoxy resin plastic package is performed on two or more than two groups of pre-packaged monomers, and the whole epoxy resin plastic package top surface is ground until the top surface of the wafer is exposed, the top surface of the wafer is coated with a high heat conduction material layer, then the wafer carrier plate is peeled off, the temporary adhesive layer adhered to the whole packaging plate is removed, and the whole packaging plate is cut according to the design size of the packaging monomers, so that the packaging monomers are obtained.
  3. 3. The pre-packaged panel-level package of claim 1, wherein the number of wafers in the pre-package unit is two or more than two, and the two or more than two groups of wafers are soldered to the top pad of the substrate through the bottom pad and are soldered to the circuit board substrate as a whole to form the pre-package unit.

Description

Pre-packaged panel-level package Technical Field The invention relates to the technical field of semiconductor packaging, in particular to a packaging method for panel-level array plastic packaging by adopting pre-packaging monomers and a packaging structure formed by the packaging method. To Panel Level (PLP) packaging technology. Background Panel Level Packaging (PLP) is a semiconductor packaging technology using a rectangular panel as a carrier, and improves production efficiency and reduces cost by a larger-sized substrate. The technology can replace the traditional 300mm wafer by adopting a rectangular wafer carrier plate with the diameter of 500mm multiplied by 500mm or even larger, the number of single-time encapsulated chips is greatly improved, and the technology is particularly suitable for mass production scenes. The method has the core advantages of higher area utilization rate and less edge waste, and can reuse the existing PCB production line equipment. However, the existing panel-level packaging process is complex, the requirement on alignment precision is extremely high, the equipment cost is very high, the final chip cost is high due to the fact that chip-level process equipment is adopted for interlayer connection, the cost is higher than that of the traditional packaging, the existing panel-level packaging process is limited, high current is difficult to achieve, and in addition, for the application of heat dissipation treatment on the back of a chip, the integration degree of the traditional process is low, and the flow is complicated. Therefore, how to provide a packaging method and structure that can simplify the panel-level packaging process, improve the packaging efficiency and yield, reduce the panel-level packaging cost, and facilitate the integration of advanced heat dissipation schemes is a technical problem to be solved in the art. Disclosure of Invention In order to solve the above problems, the present invention provides a pre-packaged panel-level package, which integrates a wafer and a circuit board substrate into a pre-packaged unit in advance, and then performs panel-level integral plastic packaging in an array form, so as to simplify the process, improve the production efficiency and yield, and facilitate the heat dissipation treatment of the back surface of a chip. The invention provides a pre-packaged panel-level package, which comprises a wafer, a circuit board substrate, a wafer carrier plate, a temporary bonding layer, an epoxy resin packaging layer and a pre-packaging matrix, wherein the bottom surface of the wafer is provided with bonding pads, the circuit board substrate consists of a top circuit layer, an insulating plate core layer and a bottom circuit layer, the top circuit layer is provided with substrate top bonding pads corresponding to the bonding pads of the bottom surface of the wafer, the packaging bonding pads and the substrate top bonding pads are respectively corresponding to each other and are connected through holes of the insulating plate core layer, the wafer is welded to the substrate top bonding pads through the bottom surface bonding pads and is integrally welded with the circuit board substrate to form pre-packaging monomers, the bonding pads of the bottom surface of the wafer are connected with the packaging bonding pads arranged on the bottom circuit board substrate through the top circuit layer and through holes of the insulating plate core layer, two or more than two wafers are prepared into a group of pre-packaging monomers, the wafer carrier plate is coated on the top surface of the wafer carrier plate, the temporary bonding layer is coated on the packaging matrix is respectively corresponding to the top surface of the substrate top circuit layer, the packaging bonding pads are respectively corresponding to the pre-packaging bonding pads through holes of the bottom surface bonding pads, the bonding pads are arranged on the top surface of the insulating plate core layer, and the temporary bonding pads are coated on the wafer carrier plate according to set coordinates, and the whole packaging monomers are cut and the whole packaging matrix is removed, and the whole packaging matrix is glued to form the whole packaging matrix is packaged by the packaging matrix. Preferably, after the whole epoxy resin plastic package and the curing are carried out on two or more than two groups of pre-packaged monomers, the whole epoxy resin plastic package top surface is ground until the top surface of the wafer is exposed, the top surface of the wafer is coated with a high heat conduction material layer, then the wafer carrier plate is peeled off, the temporary adhesive layer adhered by the whole packaging plate is removed, and the whole packaging plate is cut according to the design size of the packaging monomers, so that the packaging monomers are obtained. Preferably, the wafers arranged in the pre-packaging unit are two or more than two groups of wafer