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CN-121985875-A - Hybrid bonding three-dimensional integration method of organic medium

CN121985875ACN 121985875 ACN121985875 ACN 121985875ACN-121985875-A

Abstract

The invention discloses a hybrid bonding three-dimensional integration method of an organic medium, which belongs to the field of integrated circuit packaging, wherein a wafer level fan-out packaging process is used for reconstructing a plurality of heterogeneous chips, and a wafer level rewiring process is used for completing preparation of surface interconnection lines. And opening a window at the organic medium layer at the bonding pad of the lower layer wafer to leak out of the bonding pad to form a concave structure. The upper wafer and the lower wafer are bonded in a hybrid mode through alignment and hot pressing. Meanwhile, the surfaces of the organic medium layers of the upper and lower wafers are fully contacted and bonded together through hot pressing, so that a complex bottom filling process is not required to be introduced, the processing steps are simplified, and the production cost is reduced.

Inventors

  • XIA CHENHUI
  • LIU SHULI
  • WANG GANG
  • JI YONG

Assignees

  • 中国电子科技集团公司第五十八研究所

Dates

Publication Date
20260505
Application Date
20260129

Claims (9)

  1. 1. The hybrid bonding three-dimensional integration method of the organic medium is characterized by comprising the following steps of: S1, providing a first split bare chip (101), and carrying out wafer-level reconstruction on the first bare chip (101) through plastic packaging materials to form a first plastic packaging wafer (102); S2, sequentially forming a first dielectric layer (103) and a first metal layer (104) on the surface of a first plastic package wafer (102) through a wafer level rewiring process, and forming a first bonding pad (105) on the surface of the first dielectric layer (103) through an electroplating process; S3, forming a first solder ball (106) on the first bonding pad (105) through a wafer-level bump process; s4, leveling the surface morphology of the first solder balls (106) on the surface of the first plastic package wafer (102) through chemical mechanical polishing, cleaning the surface of the first plastic package wafer (102), removing impurities on the surface of the wafer and oxides on the surface of the first solder balls (106), and carrying out wafer activation treatment on the surface of the first plastic package wafer (102); S5, providing a second scratched bare chip (107) and a scratched vertical via interposer (108); s6, carrying out wafer level reconstruction on the second bare chip (107) and the vertical via adapter plate (108) through plastic packaging materials to form a second plastic packaging wafer (109); S7, sequentially forming a second dielectric layer (110) and a second metal layer (111) on the surface of a second plastic package wafer (109) through a wafer level rewiring process, and windowing the surface of the wiring layer to form a second bonding pad (112); S8, aligning and bonding the first plastic package wafer (102) and the second plastic package wafer (109) through a high-precision wafer hot-press bonding process to form a bonding wafer (113) structure with two layers of stacked wafers; s9, turning over the bonding wafer (113), and thinning the back surface of the second plastic package wafer (109) through a wafer thinning process to leak out a metal via (114) in the vertical via adapter plate (108); S10, sequentially forming a third dielectric layer (115) and a third metal layer (116) on the surface of a bonding wafer (113) through a wafer level rewiring process, and forming a third bonding pad (117) on the surface of the third dielectric layer (115) through an electroplating process; S11, turning over the bonding wafer (113), forming a second solder ball (118) at a third bonding pad (117) through a wafer-level bonding pad process, and finally dividing the second solder ball into single packages through a wafer dicing process to complete the three-dimensional integrated stacked package of various core particle hybrid bonding.
  2. 2. The hybrid bonding three-dimensional integration method of organic media according to claim 1, wherein the substrate material of the first bare chip (101) is silicon-based, gallium arsenide, gallium nitride, indium phosphide or silicon germanium, the thickness of the first bare chip (101) is not less than 50 μm, the material of the plastic package is liquid epoxy plastic package, particle epoxy plastic package or film plastic package, and the thickness of the first plastic package wafer (102) is not less than 50 μm.
  3. 3. The hybrid bonding three-dimensional integration method of organic media according to claim 1, wherein the material of the first dielectric layer (103) is polyimide, benzocyclobutene, polybenzoxazole, epoxy or acrylic resin organic material, the thickness of the first dielectric layer (103) is 10nm-1mm, the material of the first metal layer (104) comprises one or more of nickel, copper, gold, silver and aluminum, the thickness of the first metal layer (104) is not less than 0.1 μm, the material of the first bonding pad (105) comprises one or more of nickel, copper, gold, silver, aluminum, tin and lead, and the thickness of the first bonding pad (105) is not less than 0.1 μm.
  4. 4. The method of claim 1, wherein the wafer-level bonding pad is prepared by electroplating bumps, ball-plating bumps or printing solder, the material of the first solder balls (106) comprises one or more of nickel, copper, gold, silver, aluminum, tin and lead, and the diameter of the first solder balls (106) is 10nm-1mm.
  5. 5. The hybrid bonding three-dimensional integration method of organic media according to claim 1, wherein the chemical mechanical polishing is to polish the surface of the wafer with high precision to make the surface have a specific morphology, so that the first bonding pad is higher than the surface of the first dielectric layer; The solution for cleaning the first plastic package wafer (102) and the second plastic package wafer (109) comprises sulfuric acid, hydrochloric acid, nitric acid, citric acid or a mixed solution thereof, the activation treatment of the first plastic package wafer (102) and the second plastic package wafer (109) comprises activation by using a plasma and wet chemical method, the plasma activation specifically comprises plasma activation by nitrogen, oxygen, argon or a mixed gas thereof, and the wet chemical method comprises activation by sulfuric acid, nitric acid, hydrogen peroxide or a mixed solution thereof.
  6. 6. The hybrid bonding three-dimensional integration method of organic media according to claim 1, wherein the substrate material of the second bare chip (107) is silicon-based, gallium arsenide, gallium nitride, indium phosphide or silicon germanium, the thickness of the second bare chip (107) is not less than 50 μm, the vertical via interposer (108) is in the form of a through-silicon via interposer, a glass via interposer or a resin via interposer, and the thickness of the vertical via interposer (108) is not less than 50 μm.
  7. 7. The hybrid bonding three-dimensional integration method of organic media according to claim 1, wherein the wiring layer surface windowing is lithography windowing or laser windowing.
  8. 8. The method of claim 1, wherein the thermocompression bonding process comprises thermocompression direct bonding, or room temperature alignment and then annealing bonding.
  9. 9. The method for three-dimensional integration of hybrid bonding of organic media according to claim 1, wherein the wafer thinning is mechanical grinding, wet etching, dry etching or laser thinning, the metal via (114) is made of one or more of nickel, copper, gold, silver, aluminum, tin and lead, and the diameter of the metal via (114) is not smaller than 5 μm.

Description

Hybrid bonding three-dimensional integration method of organic medium Technical Field The invention relates to the technical field of integrated circuit packaging, in particular to a hybrid bonding three-dimensional integration method of an organic medium. Background As semiconductor process nodes advance below 3nm, the requirement for performance improvement cannot be met by purely transistor scaling. Three-dimensional integration technology becomes a critical path for continuing moore's law, whereas conventional solder-based interconnect technology is limited by a 20 μm (micro bump) pitch bottleneck, which makes it difficult to support the higher density vertical stacking requirements. The hybrid bonding reduces the interconnection spacing to the range of 1-20 mu m through the pad direct interconnection technology, and provides a new technical break for three-dimensional integration. The existing hybrid bonding technology is mainly based on SiO 2/Cu combination, but due to the characteristics of materials and process specificity, the application of the hybrid bonding technology in the field of organic media mainly based on fan-out type packaging is very limited. SiO 2, due to its own dielectric properties (k value of about 4.2), causes signal delays, affecting the high frequency circuit performance. And SiO 2 has a large thermo-mechanical stress (Young's modulus of about 70 GPa) and is prone to stress cracking during thermal cycling. High temperature annealing (400 ℃) is needed in the bonding process of the inorganic medium, and the bonding process is in conflict with the process penetration of the back-end of the CMOS, so that the chip is damaged. The introduction of Cu/organic polymer hybrid linkages (e.g., polyimide PI, benzocyclobutene BCB, etc.) has led to revolutionary improvements. The organic medium has lower dielectric constant (k value 2.5-3.0), and improves the signal transmission rate and the integrity. The organic medium has certain flexible buffer property (Young's modulus <5 GPa), and can absorb bonding interface particle defects and thermal stress. And has a lower temperature processing characteristic (curing temperature <250 ℃) compatible with the thermal budget constraints of the precursor process. The memory scenarios such as AI chip, HBM, etc. place an urgent need for hybrid bonding, which requires copper/dielectric hybrid bonding in backside illuminated sensors to achieve high performance of the illuminated sensor. The bonding technology with the spacing of <3 mu m is needed for stacking more than 16 layers of DRAM, and the interlayer stress can be reduced by using an organic medium, so that the processing yield is improved. The 2.5D/3D integration of the logic chip and the memory requires interface compatibility of heterogeneous materials, and the viscoelastic property of the organic medium is more suitable for a multi-material system. Disclosure of Invention The invention aims to provide a hybrid bonding three-dimensional integration method of an organic medium, which aims to solve the problems in the background technology. In order to solve the technical problems, the invention provides a hybrid bonding three-dimensional integration method of an organic medium, which comprises the following steps: S1, providing a first split bare chip (101), and carrying out wafer-level reconstruction on the first bare chip (101) through plastic packaging materials to form a first plastic packaging wafer (102); S2, sequentially forming a first dielectric layer (103) and a first metal layer (104) on the surface of a first plastic package wafer (102) through a wafer level rewiring process, and forming a first bonding pad (105) on the surface of the first dielectric layer (103) through an electroplating process; S3, forming a first solder ball (106) on the first bonding pad (105) through a wafer-level bump process; s4, leveling the surface morphology of the first solder balls (106) on the surface of the first plastic package wafer (102) through chemical mechanical polishing, cleaning the surface of the first plastic package wafer (102), removing impurities on the surface of the wafer and oxides on the surface of the first solder balls (106), and carrying out wafer activation treatment on the surface of the first plastic package wafer (102); S5, providing a second scratched bare chip (107) and a scratched vertical via interposer (108); s6, carrying out wafer level reconstruction on the second bare chip (107) and the vertical via adapter plate (108) through plastic packaging materials to form a second plastic packaging wafer (109); S7, sequentially forming a second dielectric layer (110) and a second metal layer (111) on the surface of a second plastic package wafer (109) through a wafer level rewiring process, and windowing the surface of the wiring layer to form a second bonding pad (112); S8, aligning and bonding the first plastic package wafer (102) and the second plastic package wafer (109) through