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CN-121985876-A - SiP packaging structure based on hybrid bonding process

CN121985876ACN 121985876 ACN121985876 ACN 121985876ACN-121985876-A

Abstract

The invention belongs to the technical field of chip packaging, in particular to a SiP packaging structure based on a hybrid bonding process, which comprises the following components: the packaging structure adopts a ceramic column grid array packaging mode, and the WB bare chips and the FC bare chips are interconnected by adopting a hybrid bonding process. The invention changes the bonding mode of the multi-core DSP chip with high speed, high frequency and high power consumption and the data memory chip from WB to FC, shortens the data transmission path, effectively reduces the signal attenuation and improves the heat dissipation efficiency. WB and FC are respectively matched with two surface treatment processes of the shell thickness Jin Baojin, and the high-performance and high-reliability packaging of the SiP chip is realized by combining the design rule of the packaging shell, so that the stability and the service life of the SiP chip are greatly improved.

Inventors

  • HOU XUEWEI
  • MA YANAN
  • SONG BIN
  • XI LIANG
  • WANG DANTONG
  • ZHAO XUAN

Assignees

  • 北京计算机技术及应用研究所

Dates

Publication Date
20260505
Application Date
20251228

Claims (10)

  1. 1. A SiP packaging structure based on a hybrid bonding process is characterized by comprising a plurality of WB bare chips, a plurality of FC bare chips and a plurality of passive devices, wherein the packaging structure adopts a ceramic column grid array packaging mode, and the WB bare chips and the FC bare chips are interconnected by adopting the hybrid bonding process.
  2. 2. The SiP packaging structure based on the hybrid bonding process of claim 1, wherein the WB bare chip, the FC bare chip, and the passive devices are uniformly distributed on the front surface of the ceramic package.
  3. 3. The SiP package structure of claim 1, wherein the core die is disposed in the middle of the package case or near the critical signal interface.
  4. 4. The SiP package structure of claim 1, wherein the power leads and the decoupling capacitors are disposed in close proximity in layout.
  5. 5. The SiP packaging structure based on the hybrid bonding process of claim 1 is characterized in that high-speed differential signals are distributed on the periphery of a BGA, reference ground is arranged around each group of high-speed differential signals, the same group of differential signals are distributed in the same area and take clock control signals as references, low-speed single-ended signals are nearby led out to BGA solder balls close to a leading-out end of a bare chip according to the principle of the same group of the same area, and a power plane layer and a reference ground plane are alternately arranged.
  6. 6. The SiP package structure based on the hybrid bonding process according to claim 1, further comprising two sets of EMIF parallel buses, the wiring of which satisfies the following rules: The address line, the control line and the clock line are in one group, and the data line is in the other group; If the clock signal exists, the other signal lines perform equal length processing according to the clock length, the equal length errors of the address line, the control line and the clock line are controlled within +/-50 mil, and the equal length errors of the data line are controlled within +/-100 mil; If no clock signal exists, equal length processing is carried out according to the longest line in the two groups of lines, the equal length errors of the address line and the control line are controlled within +/-50 mil, and the equal length errors of the data line are controlled within +/-100 mil; Every 8-bit address lines or data lines are arranged in the same layer.
  7. 7. The SiP package structure of claim 1 wherein the ratio of the linewidth to the line spacing of the SERDES differential signal transmission lines is 75/100.
  8. 8. The SiP packaging structure based on the hybrid bonding process of claim 1, wherein the I/O interface adopts a parallel wiring mode, and the ratio of line width to line spacing is 75/100.
  9. 9. The SiP package structure of claim 1 wherein the package stack is 24 layers, wherein, L01 is a chip bonding pad; L02, L04, L06, L08, L10, L12, L13, L15 and L16 are wiring layers; L18, L20 and L22 are power supply layers; L24 is the BALL layer; The rest is GND layer.
  10. 10. The SiP packaging structure based on the hybrid bonding process according to claim 1, wherein a thin Jin Gongyi is adopted in the FC region, the thickness of the nickel layer is 1.3-8.9 μm, the thickness of the gold layer is 0.03-0.3 μm, and a thick gold process is adopted in the WB region, the thickness of the nickel layer is 1.3-8.9 μm, and the thickness of the gold layer is 1.3-5.7 μm.

Description

SiP packaging structure based on hybrid bonding process Technical Field The invention belongs to the technical field of chip packaging, and particularly relates to a SiP packaging structure based on a hybrid bonding process. Background SiP is a very important and popular technology in today's electronic packaging technology, and has the capability of integrating bare chips with different functions (such as data memory, DSP processor, radio frequency chip, CPU, etc.) into a package by high density interconnection technology, thereby forming a complete system. When planning a high-reliability information processing (SiP) chip, comprehensive consideration needs to be carried out in the aspects of high reliability, high integration level, high performance, high economy and the like. The bonding mode of the chip has decisive influence on the above aspects. The Flip Chip (FC) realizes the electrical interconnection between the Chip and the substrate by Bonding, has excellent high-frequency high-speed performance, high heat conduction efficiency and high interconnection density, is suitable for high-density packaging, but has high cost and process threshold compared with WB. The two different interconnection modes have different requirements on the gold plating process on the surface of the pipe shell, and the high-frequency signal generally adopts thin gold, so that the cost is low, the thick gold is suitable for gold wire bonding, the cost is high, and the high-frequency signal is used for carrying high current, high power and strong bonding. Disclosure of Invention In order to solve the technical problems, the invention provides a SiP packaging structure based on a hybrid bonding process, which comprises a plurality of WB bare chips, a plurality of FC bare chips and a plurality of passive devices, wherein the packaging structure adopts a ceramic column grid array packaging mode, and the WB bare chips and the FC bare chips are interconnected by adopting the hybrid bonding process. Furthermore, the WB bare chip, the FC bare chip and the passive devices are uniformly distributed on the front surface of the ceramic tube shell. Further, the core bare chip is arranged in the middle of the packaging tube shell or near the key signal interface. Further, the power supply pins and the decoupling capacitors are arranged close to each other in layout. Furthermore, the high-speed differential signals are distributed on the periphery of the BGA, reference ground is arranged around each group of high-speed differential signals, the same group of differential signals are distributed in the same area and take clock control signals as references, low-speed single-ended signals are close to the lead-out end of the bare chip and are led out to the BGA solder balls nearby according to the principle of the same group of the same area, and the power plane layer and the reference ground plane layer are alternately arranged. Further, two sets of EMIF parallel buses are included, and the wiring of the two sets of EMIF parallel buses meets the following rules: The address line, the control line and the clock line are in one group, and the data line is in the other group; If the clock signal exists, the other signal lines perform equal length processing according to the clock length, the equal length errors of the address line, the control line and the clock line are controlled within +/-50 mil, and the equal length errors of the data line are controlled within +/-100 mil; If no clock signal exists, equal length processing is carried out according to the longest line in the two groups of lines, the equal length errors of the address line and the control line are controlled within +/-50 mil, and the equal length errors of the data line are controlled within +/-100 mil; Every 8-bit address lines or data lines are arranged in the same layer. Further, the ratio of the linewidth to the line spacing of the SERDES differential signal transmission line is 75/100. Furthermore, the I/O interface adopts a parallel wiring mode, and the ratio of the line width to the line spacing is 75/100. Further, the package stack is 24 layers, wherein, L01 is a chip bonding pad; L02, L04, L06, L08, L10, L12, L13, L15 and L16 are wiring layers; L18, L20 and L22 are power supply layers; L24 is the BALL layer; The rest is GND layer. Further, a thin Jin Gongyi is adopted in the FC region, the thickness of the nickel layer is 1.3-8.9 mu m, the thickness of the gold layer is 0.03-0.3 mu m, a thick gold process is adopted in the WB region, the thickness of the nickel layer is 1.3-8.9 mu m, and the thickness of the gold layer is 1.3-5.7 mu m. The invention changes the bonding mode of the multi-core DSP chip with high speed, high frequency and high power consumption and the data memory chip from WB to FC, shortens the data transmission path, effectively reduces the signal attenuation and improves the heat dissipation efficiency. WB and FC are respectively matched with two