CN-121985877-A - Three-dimensional stacked chip with closed-loop layered microfluid temperature control structure and closed-loop temperature control method

CN121985877ACN 121985877 ACN121985877 ACN 121985877ACN-121985877-A

Abstract

The invention relates to a three-dimensional stacked chip with a closed-loop layered microfluid temperature control structure and a closed-loop temperature control method. By adopting a sensing-radiating-interconnecting integrated periodic array architecture, the functions of temperature sensing, fluid radiating and vertical interconnecting are coordinated. The distributed temperature sensing system monitors the temperature of each area of the chip in real time through the PN junction diode array, the intelligent control unit generates a regulating and controlling instruction based on a layered partition control algorithm, and accurate flow regulation of each layer of micro flow channels is achieved through an independently controlled micro valve and a variable rate micro pump. The system builds a complete closed-loop control framework from sensing, decision making to execution, breaks through the limitation of the traditional heat dissipation scheme in the aspects of dynamic response and management precision, realizes intelligent fine temperature control of three-dimensional stacked chips, and remarkably improves the heat dissipation efficiency and operation reliability of the chips.

Inventors

HE YURONG
Chen Junni
TANG TIANQI
LIANG YIXIN
ZHANG BORUI

Assignees

哈尔滨工业大学

Dates

Publication Date: 20260505
Application Date: 20260123

Claims (10)

1. The three-dimensional stacked chip with the closed-loop layered microfluid temperature control structure is characterized by being formed by combining a multi-layer chip stacked structure, an embedded microchannel network, a distributed temperature sensing system, a mixed Through Silicon (TSV) interconnection array and an intelligent control unit, wherein the multi-layer chip stacked structure comprises a packaging shell (1), a cooling liquid inlet (2), a cooling liquid outlet (3) and a chip layer (4), the embedded microchannel network covers a microchannel substrate (5), a micro valve (6) and a waveform microchannel (10), the distributed temperature sensing system is formed by a plurality of PN TSV diodes (9), the mixed TSV interconnection array comprises an electric TSV (7), a thermal management TSV (TTSV) (8), the electric TSV (7) and TTSV (8) form a mixed cluster (11), and the intelligent control unit comprises a digital sensor hub (12), a signal conditioning and analog-digital conversion circuit (13), a decision and control center (14), a water pump (15) and a valve controller (16).
2. The three-dimensional stacked chip of claim 1, wherein TTSV is filled with a diamond-metal composite material, wherein the volume fraction of diamond particles is between 50% and 80%.
3. The three-dimensional stacked chip of claim 2, wherein the composite material is a copper-diamond composite material or a silver-diamond composite material.
4. The three-dimensional stacked chip of claim 1, wherein the wavy micro-channels are of a wavy structure etched on the micro-channel substrate, and the micro-valves are arranged at inlets of the micro-channels of each layer and used for independently regulating the flow of the cooling liquid.
5. The three-dimensional stacked chip of claim 1, wherein said PN junction diodes are disposed between adjacent microchannels, the outputs of which are connected to said digital sensor hub by metal wires.
6. The three-dimensional stacked chip of claim 1, wherein the decision and control hub is a microcontroller with built-in algorithm periodically executing the steps of collecting full chip temperature data and constructing a three-dimensional thermal profile, identifying a temperature region exceeding a preset threshold, and calculating PWM control amounts corresponding to the micro-valves and power adjustment instructions of the micro-pumps.
7. The three-dimensional stacked chip of claim 1, wherein the intelligent control unit further comprises a fault monitoring module for triggering a safety protection procedure when a temperature or flow anomaly is detected.
8. The three-dimensional stacked chip of claim 1, wherein in the hybrid TSV cluster, the electrical TSVs and TTSV are arranged at 1:1 intervals to form a periodic thermo-electrical synergistic interconnect structure.
9. A closed-loop temperature control method based on the three-dimensional stacked chips of any one of claims 1 to 7 is characterized by acquiring a chip temperature field in real time by means of a distributed temperature sensor array, identifying and positioning hot spot areas based on a layered partition control strategy, independently adjusting the opening of micro valves and the power of a system micro pump of a corresponding level of the hot spot areas to change local coolant flow, and dynamically adjusting control parameters according to temperature feedback to realize closed-loop temperature control.
10. The method of claim 9, wherein the failsafe procedure of full valve opening, pump power maximization, and alarm triggering is performed upon detecting a temperature exceeding a safety threshold.

Description

Three-dimensional stacked chip with closed-loop layered microfluid temperature control structure and closed-loop temperature control method Technical Field The invention belongs to the technical field of semiconductor packaging and integrated circuit thermal management, and particularly relates to an intelligent three-dimensional stacked chip temperature control system and method with dynamic sensing and accurate regulation functions. Background Three-dimensional stacking technology is considered one of the key ways to continue moore's law evolution, however its development is facing serious thermal management challenges. The power density is obviously improved due to the vertical integrated structure of the multi-layer chip, and the heat radiation path from the middle layer device to the packaging shell is prolonged, so that the heat resistance is increased, and the local high-temperature area is difficult to effectively eliminate. The external heat dissipation means commonly adopted at present comprises heat dissipation fins, a temperature equalization plate and a package-level liquid cooling technology, and essentially belongs to a global uniform heat dissipation strategy, and the fine regulation and control capability on the temperature distribution of the inner space of the stacked structure is lacking. Although the prior researches have attempted to integrate micro-channel structures inside chips to improve heat dissipation efficiency, there are several key technical bottlenecks. First, the temperature sensing unit and the cooling actuator are independent of each other in spatial layout, resulting in significant delay in the thermal response of the system, and difficult to construct an effective dynamic closed-loop control mechanism. In addition, as the heat dissipation structures such as micro-channels and heat conduction through holes and the electric interconnection through holes lack of cooperative optimization in layout design, the coupling interference phenomenon between the thermal-electric-current multi-physical fields is prominent, so that the heat transfer efficiency is affected, and the performance degradation and the reliability degradation of the device can be caused by thermal stress concentration or electromagnetic interference. Secondly, the regulation granularity of the existing temperature control system is still limited to the chip or hierarchy scale, accurate positioning and on-demand heat dissipation of sub-regional hot spots cannot be realized, and the dynamic management requirement of a high-performance computing chip on a non-uniform thermal field is difficult to meet. Therefore, there is a strong need in the art for a sophisticated dynamic thermal management scheme that enables integrated, thermo-electro-flow co-design of three-dimensional stacked chip internal awareness-implementation. Disclosure of Invention The invention aims to overcome the technical limitations of insufficient sensing and execution separation, insufficient thermal management precision, incapability of coping with dynamic thermal load and the like in the existing three-dimensional stacked chip heat dissipation scheme, and provides a closed-loop temperature control system with real-time sensing, intelligent decision making and accurate execution capabilities. In order to achieve the above object, the present invention adopts the following technical scheme: A three-dimensional stacked chip intelligent temperature control system mainly comprises a multi-layer chip stacked structure, an embedded micro-channel network, a distributed temperature sensing system, a mixed Through Silicon Via (TSV) interconnection array and an intelligent control unit. The multi-layer chip stacking structure comprises a packaging shell, a cooling liquid inlet, a cooling liquid outlet and a chip layer. The embedded micro-channel network covers the micro-channel substrate, the micro-valve and the waveform micro-channel. The distributed temperature sensing system is composed of a plurality of PN junction diodes. The hybrid TSV interconnect array includes electrical TSVs, thermal management TSVs (TTSVs), the electrical TSVs and TTSV comprising a hybrid TSV cluster. The intelligent control unit comprises a digital sensor hub, a signal conditioning and analog-to-digital conversion circuit, a decision and control center, a water pump and a valve controller. The method is characterized in that a perception-heat dissipation-interconnection integrated periodic array architecture is adopted, and the collaborative management and closed-loop control of multiple physical fields are achieved through a modularized design. Furthermore, the packaging shell packages the whole three-dimensional stacked chips, cooling liquid flows in from the cooling liquid inlet and flows out from the cooling liquid outlet, and the chip layer is a main functional area and a heating area of the chips. Furthermore, the waveform micro-channel is mainly etched on the micro