CN-121986296-A - Array substrate, display panel and display device

Abstract

The array substrate, the display panel and the display device comprise a substrate, wherein the substrate comprises a display area, a first non-display area, a second non-display area, a third non-display area, a common electrode bus and a feedback line, the first non-display area is located on one side of the display area and used for being bound with a driving circuit, the second non-display area is located on the display area and far away from the first non-display area, the third non-display area is connected with the first non-display area and the second non-display area, the common electrode bus at least partially surrounds the display area, the feedback line extends from the first non-display area to the second non-display area through the third non-display area, and the feedback line is electrically connected with the common electrode bus in the second non-display area.

Inventors

• WANG GUANGXING
• JIANG LIFANG
• YAN JINGLONG
• DONG DIANZHENG
• CUI XIAOPENG
• DIAO KAI
• SUN HANYAN
• MA ZHIQIANG
• YANG YUE
• LIU JIANTAO

Assignees

• 京东方科技集团股份有限公司
• 北京京东方显示技术有限公司

Dates

Publication Date

20260505

Application Date

20240819

Claims (20)

1. An array substrate, comprising: The display device comprises a substrate base plate, a first display module and a second display module, wherein the substrate base plate comprises a display area, a first non-display area which is positioned at one side of the display area and is used for being bound with a driving circuit, a second non-display area which is positioned at the display area and is far away from the first non-display area, and a third non-display area which is connected with the first non-display area and the second non-display area; a common electrode bus disposed at least partially surrounding the display area; And a feedback line extending from the first non-display region to the second non-display region through the third non-display region, and electrically connected with the common electrode bus line in the second non-display region.
2. The array substrate of claim 1, wherein the feedback line is electrically connected to the common electrode bus line at an intermediate region of the second non-display region.
3. The array substrate of claim 2, further comprising a shorting ring in the second non-display region, the feedback line electrically connected to the common electrode bus line across the shorting ring.
4. The array substrate of claim 2, further comprising a shorting ring in the second non-display region, the shorting ring including a break, the feedback line electrically connected to the common electrode bus line through the break.
5. The array substrate of claim 4, further comprising a plurality of electrostatic discharge structures electrically connected to the shorting ring, the feedback line being electrically connected to the electrostatic discharge structures.
6. The array substrate of claim 1, wherein the feedback line is electrically connected to the common electrode bus line at an end region near the second non-display region.
7. The array substrate of any one of claims 1 to 6, further comprising a first common electrode line electrically connected to the common electrode bus line in the first non-display region.
8. The array substrate of claim 7, wherein the first common electrode line includes a first sub common electrode line electrically connected to the common electrode bus line in a middle region of the first non-display region.
9. The array substrate of claim 7 or 8, wherein the first common electrode line includes a second sub common electrode line electrically connected to the common electrode bus line at an end region near the first non-display region.
10. The array substrate of claim 9, wherein the second sub-common electrode line is externally connected to a power management chip.
11. The array substrate of any one of claims 7 to 9, wherein the feedback line is electrically connected to the first common electrode line through the external operational amplifier.
12. The array substrate of claim 11, wherein the first common electrode lines are plural, and different ones of the first common electrode lines are electrically connected to different ones of the operational amplifiers.
13. The array substrate of claim 12, wherein the feedback lines are two, and the first common electrode lines are an even number; The two feedback lines are symmetrical about a central axis extending along a first direction of the display area, and the even number of the first common electrode lines are symmetrical about a central axis extending along the first direction of the display area, wherein the first direction is an arrangement direction of the first non-display area and the second non-display area.
14. The array substrate of claim 11, wherein the first common electrode lines are plural, and at least a part of the first common electrode lines share one operational amplifier.
15. The array substrate of claim 14, further comprising a dummy line symmetrical to at least a portion of the feedback line about a central axis of the display region extending in a first direction, the first direction being an arrangement direction of the first non-display region and the second non-display region.
16. The array substrate of any one of claims 1-15, wherein the third non-display region comprises a gate driving circuit region; The array substrate further comprises a shielding line and a clock signal line arranged in the grid driving circuit area, wherein the shielding line extends from between the clock signal line and the feedback line to between the grid driving circuit area and the common electrode bus.
17. The array substrate of claim 16, wherein an impedance of the feedback line is smaller than an impedance of the shielding line, and a line width of the feedback line is larger than a line width of the shielding line in the second non-display region.
18. The array substrate of any one of claims 1 to 17, further comprising a plurality of second common electrode lines and a plurality of data lines in the display area, wherein each two adjacent data lines are a group, and the second common electrode lines are located between each group of the data lines.
19. The array substrate of claim 18, further comprising a plurality of pixel electrodes arranged in an array at the display area; The data lines are positioned at part of column gaps of the pixel electrodes, and the second common electrode lines are arranged at the column gaps among the groups of data lines; the column gap width of the data line and the second common electrode line is larger than the column gap width of the pixel electrode between two data lines in a group.
20. A display panel, comprising an array substrate and a counter substrate disposed opposite to each other, wherein the array substrate is the array substrate according to any one of claims 1 to 19.

Description

Array substrate, display panel and display device Technical Field The disclosure relates to the technical field of display, in particular to an array substrate, a display panel and a display device. Background The thin film transistor liquid crystal display (Thin Film Transistor Liquid CRYSTAL DISPLAY, TFT-LCD) has the characteristics of small size, low power consumption, high image quality, no radiation, portability, etc., has been rapidly developed in recent years, has gradually replaced the conventional cathode ray tube display device (Cathode Ray Tube display, CRT), and has been dominant in the current flat panel display market. At present, TFT-LCDs are widely used in various large, medium and small-sized products, and almost cover the main electronic products of the current information society, such as liquid crystal televisions, high definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigators, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and illusive displays. Disclosure of Invention The array substrate, the display panel and the display device provided by the disclosure have the following specific schemes: In one aspect, an array substrate provided in an embodiment of the present disclosure includes: The display device comprises a substrate base plate, a first display module and a second display module, wherein the substrate base plate comprises a display area, a first non-display area which is positioned at one side of the display area and is used for being bound with a driving circuit, a second non-display area which is positioned at the display area and is far away from the first non-display area, and a third non-display area which is connected with the first non-display area and the second non-display area; a common electrode bus disposed at least partially surrounding the display area; And a feedback line extending from the first non-display region to the second non-display region through the third non-display region, and electrically connected with the common electrode bus line in the second non-display region. In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the feedback line is electrically connected to the common electrode bus line in a middle area of the second non-display area. In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the feedback line further includes a shorting ring located in the second non-display area, and the feedback line is electrically connected to the common electrode bus line across the shorting ring. In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a shorting ring located in the second non-display area, where the shorting ring includes a break, and the feedback line is electrically connected to the common electrode bus through the break. In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the array substrate further includes a plurality of electrostatic discharge structures electrically connected to the shorting ring, and the feedback line is electrically connected to the electrostatic discharge structures. In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the feedback line is electrically connected to the common electrode bus line at an end region near the second non-display region. In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, a first common electrode line is further included, where the first common electrode line is electrically connected to the common electrode bus line in the first non-display area. In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the first common electrode line includes a first sub common electrode line, and the first sub common electrode line is electrically connected to the common electrode bus line in a middle area of the first non-display area. In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the first common electrode line includes a second sub common electrode line, and the second sub common electrode line is electrically connected to the common electrode bus line at an end region near the first non-display region. In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the second sub-common electrode line is externally connected to a power management chip. In some embodiments, in the above array substrate provided in the embodiments of the present disclosure, the feedback line is electrically connected to the first common electrode line through the external operational amplifier. In some em