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CN-121986324-A - Programming enhanced baseboard management controller

CN121986324ACN 121986324 ACN121986324 ACN 121986324ACN-121986324-A

Abstract

Techniques for integrating a Programmable Logic Device (PLD) into a Baseboard Management Controller (BMC) are described herein. The program-enhanced BMC is powered on by a PLD that is integrated into the program-enhanced BMC and that is coupled to an internal bus of the program-enhanced BMC. The configuration file is provided to the PLD from immutable BMC hardware in the BMC based at least on the programming enhanced BMC being powered on. The configuration file specifies the configuration of programmable hardware to be programmatically applied to the PLD. The programmable hardware of the PLD is programmed by loading the configuration file such that the programmable hardware natively presents the peripheral interface defined by the configuration file on the internal bus of the programming-enhanced BMC.

Inventors

  • B.D. Kelly
  • P.HUANG

Assignees

  • 微软技术许可有限责任公司

Dates

Publication Date
20260505
Application Date
20241017
Priority Date
20240105

Claims (20)

  1. 1. A programming enhanced Baseboard Management Controller (BMC) (104,300,492) comprising: an immutable BMC hardware (108, 308), the immutable BMC hardware (108, 308) configured to perform a system management operation with respect to a peripheral device (106) external to the program enhanced BMC (104,300,492); internal bus (114,314) A Programmable Logic Device (PLD) (110, 310), the Programmable Logic Device (PLD) (110, 310) coupled to the internal bus (114,314), the PLD configured to power on (202) the programming-enhanced BMC (104,300,492); Wherein the immutable BMC hardware (108, 308) is configured to provide (204) a configuration file (326) to the PLD (110, 310) based at least on the programming-enhanced BMC (104,300,492) being powered on, the configuration file (326) specifying a configuration of programmable hardware (320) to be programmatically applied to the PLD (110, 310), and Wherein the PLD (110, 310) is further configured to program (206) the programmable hardware (320) of the PLD (110, 310) by loading the configuration file (326) such that the programmable hardware (320) natively presents a peripheral interface (116, 316) defined by the configuration file (326) on the internal bus (114,314) of the programming-enhanced BMC (104,300,492).
  2. 2. The program enhanced BMC of claim 1, wherein the PLD is configured to power on the program enhanced BMC despite an initial configuration file defining an initial configuration to be applied to the PLD before the program enhanced BMC is powered on.
  3. 3. The program enhanced BMC of claim 1, wherein the PLD is configured to power on the program enhanced BMC despite the PLD not having access to an initial configuration file defining an initial configuration to be applied to the PLD before the program enhanced BMC is powered on.
  4. 4. The programming-enhanced BMC of claim 1, wherein the immutable BMC hardware is configured to provide packets via the peripheral interface, the packets being formatted according to a protocol associated with the peripheral interface.
  5. 5. The programming-enhanced BMC of claim 4, wherein the immutable BMC hardware is configured to provide the packet without the packet being converted to another protocol according to which the packet is formatted.
  6. 6. The programming-enhanced BMC of claim 1, wherein the PLD is configured to load the configuration file by creating a register definition that defines the peripheral interface, and Wherein the programmable hardware is configured to natively present the register definition on the internal bus of the programming-enhanced BMC to provide the peripheral interface.
  7. 7. The programming-enhanced BMC of claim 1, wherein the PLD causes an Operating System (OS) executing on the programming-enhanced BMC to natively detect the peripheral interface by loading the configuration file.
  8. 8. A method, comprising: Powering on a programming enhanced Baseboard Management Controller (BMC) (104,300,492) by a Programmable Logic Device (PLD) (110, 310), the Programmable Logic Device (PLD) (110, 310) being integrated into the programming enhanced BMC (104,300,492) and being coupled to an internal bus (114,314) of the programming enhanced BMC; Providing (204) a configuration file (326) from immutable BMC hardware (108, 308) in the program-enhanced BMC (104,300,492) to the PLD (110, 310) based at least on the program-enhanced BMC (104,300,492) being powered on, the configuration file (326) specifying a configuration of programmable hardware (320) to be programmatically applied to the PLD (110, 310), and Programming (206) the programmable hardware (320) of the PLD (110, 310) by loading the configuration file (326) such that the programmable hardware (320) natively presents a peripheral interface (116, 316) defined by the configuration file (326) on the internal bus (114,314) of the programming-enhanced BMC (104,300,492).
  9. 9. The method of claim 8, wherein powering on the programming-enhanced BMC comprises: A power-on sequence is performed by the PLD in which the PLD powers on the programming-enhanced BMC despite a corruption of an initial configuration file defining an initial configuration to be applied to the PLD during the power-on sequence.
  10. 10. The method of claim 8, wherein powering on the programming-enhanced BMC comprises: A power-on sequence is performed by the PLD in which the PLD powers on the programming-enhanced BMC despite not having access to an initial configuration file during the power-on sequence, the initial configuration file defining an initial configuration to be applied to the PLD.
  11. 11. The method of claim 8, further comprising: Packets are provided from the immutable BMC hardware to a peripheral device via the peripheral interface, the packets being formatted according to a protocol associated with the peripheral interface.
  12. 12. The method of claim 11, wherein providing the packet comprises: Providing the packet from the immutable BMC hardware to the peripheral device via the peripheral interface without the packet being converted to another protocol in the transfer to the peripheral device, the packet being formatted according to the protocol associated with the peripheral interface.
  13. 13. The method of claim 8, wherein loading the configuration file comprises: loading the configuration file by creating a register definition defining the peripheral interface, and Wherein the programmable hardware of the PLD is programmed such that the register definitions are natively presented on the internal bus of the programming-enhanced BMC to provide the peripheral interface.
  14. 14. The method of claim 8, wherein programming the programmable hardware of the PLD causes an Operating System (OS) executing on the programming-enhanced BMC to natively detect the peripheral interface.
  15. 15. A computing system (100,402,500) comprising: a memory (420,422,424,504); A processing system (410,502), the processing system (410,502) being coupled to the memory (420,422,424,504), and A programming enhanced Baseboard Management Controller (BMC) (104,300,492) comprising: An internal bus (114,314); -a non-variable peripheral interface (112, 312), the non-variable peripheral interface (112, 312) being coupled to the internal bus (114,314); -non-variable BMC hardware (108, 308), the non-variable BMC hardware (108, 308) being configured to perform a system management operation with respect to a peripheral device (106) by providing a packet (332) to the peripheral device (106) via the non-variable peripheral interface (112, 312), the peripheral device (106) comprising the memory (420,422,424,504) or the processing system (410,502), and A Programmable Logic Device (PLD) (110, 310), the PLD (110, 310) coupled to the internal bus (114,314), the PLD (110, 310) configured to power on the programming-enhanced BMC (104,300,492), the PLD (110, 310) comprising programmable hardware (320); Wherein the immutable BMC hardware (108, 308) is further configured to provide (204) a configuration file (326) to the PLD (110, 310) based at least on the program enhanced BMC (104,300,492) being powered on, the configuration file (326) specifying a configuration of the programmable hardware (320) to be programmatically applied to the PLD (110, 310), and Wherein the PLD (110, 310) is further configured to program (206) the programmable hardware (320) of the PLD (110, 310) by using the configuration file (326) to natively provide a programmed peripheral interface (116, 316) on the internal bus (114,314) of the programming-enhanced BMC (104,300,492).
  16. 16. The computing system of claim 15, wherein the PLD is configured to perform a power-on sequence in which the PLD powers on the programming-enhanced BMC despite an initial configuration file being corrupted, the initial configuration file defining an initial configuration to be applied to the PLD during the power-on sequence.
  17. 17. The computing system of claim 15, wherein the PLD is configured to perform a power-on sequence in which the PLD powers on the programming-enhanced BMC despite not having access to an initial configuration file during the power-on sequence, the initial configuration file defining an initial configuration to be applied to the PLD.
  18. 18. The computing system of claim 15, wherein the immutable BMC hardware is configured to provide packets via the programmed peripheral interface, the packets being formatted according to a protocol associated with the programmed peripheral interface.
  19. 19. The computing system of claim 18, wherein the immutable BMC hardware is configured to provide the packet without the packet being converted to another protocol according to which the packet is formatted.
  20. 20. The computing system of claim 15, wherein the PLD is configured to program the programmable hardware of the PLD by creating a register definition that defines the peripheral interface using the configuration file, and Wherein the programmable hardware is configured to natively present the register definition on the internal bus of the programming-enhanced BMC to provide the programmed peripheral interface.

Description

Programming enhanced baseboard management controller Cross Reference to Related Applications The application claims the benefit of U.S. provisional application serial No. 63/597,680 filed on 11/9 of 2023, and entitled "Programming-Enhanced Baseboard Management Controller," the entire contents of which are incorporated herein by reference. Background Baseboard Management Controllers (BMCs) are typically implemented as discrete components on a motherboard of a computing device, such as a server, to perform system management operations with respect to the computing device. For example, the BMC may monitor parameters of a component (also referred to as a "monitored component") that is included in the computing device and provide an alert to a user (e.g., a system administrator) if the parameters exceed established boundaries. Examples of such parameters include temperature, cooling fan speed, power state, and Operating System (OS) state. Complex Programmable Logic Devices (CPLDs) or Field Programmable Gate Arrays (FPGAs) are typically implemented as another discrete component on a computing device motherboard to translate signals from a protocol associated with the BMC to a protocol associated with the motherboard and the components being monitored. Converting signals in this manner consumes a significant amount of time and resources. Traditional discrete BMCs and CPLD/FPGAs have relatively complex interdependencies. For example, CPLD/FPGA relies on BMC for update and recovery, and BMC relies on CPLD/FPGA powering on BMC and performing protocol conversions as described above. BMCs and CPLD/FPGAs have traditionally exhibited incompatible recovery mechanisms, which create weaknesses in computing devices. Furthermore, implementing the BMC and CPLD/FPGA as separate discrete components results in relatively high packaging costs and relatively large footprints on the motherboard. Disclosure of Invention It may be desirable to integrate a Programmable Logic Device (PLD) into the BMC. PLDs are electronic components used to build reconfigurable circuits (e.g., reconfigurable digital circuits). For example, a PLD may have undefined functions at the time of manufacture, and the PLD may then be programmed to have the desired functions, which enable the PLD to be used in circuitry. According to this example, programming the PLD may change the connections between the gates of the PLD to achieve the desired functionality. Examples of PLDs include, but are not limited to, simple Programmable Logic Devices (SPLDs), complex Programmable Logic Devices (CPLDs), and Field Programmable Gate Arrays (FPGAs). Examples of SPLDs include, but are not limited to, programmable Array Logic (PAL), programmable Logic Array (PLA), and Generic Array Logic (GAL). By integrating the PLD into the BMC, signal transitions from the protocol of the BMC to the protocol of the motherboard on which the BMC is implemented and to the protocol of the component monitored by the BMC may be avoided. Integrating the PLD into the BMC enables the PLD to power on the BMC even if an image of the PLD (e.g., a configuration file defining the configuration of the PLD) is corrupted or absent. Furthermore, various methods for integrating a PLD into a BMC are described herein. Integrating the PLD into the BMC enables the PLD to natively present the programmed peripheral interface on the internal bus of the BMC. The peripheral interface being programmed is a peripheral interface created by programming programmable hardware. In one aspect, a PLD programs its programmable hardware to provide a programmed peripheral interface. A peripheral interface is an interface that enables interaction (e.g., communication) with a peripheral device. In one aspect, a peripheral interface generated by the PLD enables the BMC to communicate with the peripheral device. The peripheral device is a device external to the BMC. Examples of peripheral devices include, but are not limited to, sensors, cooling fans, memory, power Supply Units (PSUs), processing systems, input/output (I/O) devices, trust roots, chassis managers, and rack managers. Examples of sensors include, but are not limited to, thermometers, accelerometers, speed sensors, displacement sensors, and pressure sensors. Examples of memory include, but are not limited to, flash memory and Solid State Drives (SSDs). Examples of processing systems include, but are not limited to, central Processing Units (CPUs) and Graphics Processing Units (GPUs). Examples of I/O devices include, but are not limited to, printed circuit components (PCAs) and Network Interface Controllers (NICs). A root of trust is an authoritative entity that is presumed for trust rather than derived. A chassis manager is a system that manages resources in a computer chassis. A computer chassis is a physical computer chassis that stores hardware components of a computer. Rack managers are systems that manage computer racks. A computer rack is a physical structure on whic