CN-121986356-A - Semiconductor inspection system with deep neural network

Abstract

In a system such as an optical inspection system, a light source generates a light beam, a stage holds a workpiece in the path of the light beam, a detector receives the light beam reflected from the workpiece, and a processor is in electronic communication with the detector. The processor is configured to operate a deep neural network including a backbone network and a plurality of head networks connected to a top layer. Each of the head networks is configured to be used during inspection of an image of the workpiece generated using data from the detector.

Inventors

• G. Ravich

Assignees

• 奥宝科技有限公司

Dates

Publication Date

20260505

Application Date

20241115

Priority Date

20231231

Claims (20)

1. 1. A system, comprising: A light source that generates a light beam; A stage configured to hold a workpiece in a path of the beam; a detector that receives the light beam reflected from the workpiece; A processor in electronic communication with the detector, wherein the processor is configured to operate a deep neural network including a backbone network and a plurality of head networks connected to a top layer, wherein each of the head networks is configured to be used during inspection of an image of the workpiece generated using data from the detector, and An electronic data storage unit in electronic communication with the processor, wherein the deep neural network is stored on the electronic data storage unit.
2. 2. The system of claim 1, wherein each of the head networks is configured to perform image classification, image regression, object detection, dense segmentation, example segmentation, or depth estimation.
3. 3. The system of claim 1, wherein the processor is a GPU.
4. 4. The system of claim 1, wherein the processor is a CPU.
5. 5. The system of claim 1, wherein one or more of the head networks are configured to operate concurrently.
6. 6. The system of claim 1, wherein the deep neural network is configured to change between the plurality of head networks during the inspection of the image.
7. 7. The system of claim 1, wherein the workpiece is a semiconductor wafer.
8. 8. A method, comprising: Receiving an image of a workpiece at a processor, and The image is inspected using the processor, wherein the inspection uses a deep neural network, the deep via network including a backbone network and a plurality of head networks connected to a top layer, and wherein each of the head networks is configured to be used during inspection of the image.
9. 9. The method as recited in claim 8, further comprising: Directing a beam of light at the workpiece; Receiving the beam reflected from the workpiece at a detector, and Data is communicated from the detector to the processor to generate the image.
10. 10. The method of claim 8, wherein each of the head networks is configured to perform image classification, image regression, object detection, dense segmentation, example segmentation, or depth estimation.
11. 11. The method of claim 8, wherein the processor is a GPU.
12. 12. The method of claim 8, wherein the processor is a CPU.
13. 13. The method of claim 8, wherein one or more of the head networks operate concurrently.
14. 14. The method of claim 8, wherein the deep neural network is configured to change between the plurality of head networks during the inspection.
15. 15. The method of claim 8, wherein the workpiece is a semiconductor wafer.
16. 16. A non-transitory computer readable storage medium comprising one or more programs for performing the following on one or more computing devices: receiving an image of a workpiece The image is inspected using a deep neural network including a backbone network and a plurality of head networks connected to a top layer, and wherein each of the head networks is configured to be used during inspection of the image.
17. 17. The non-transitory computer-readable storage medium of claim 16, wherein each of the head networks is configured to perform image classification, image regression, object detection, dense segmentation, example segmentation, or depth estimation.
18. 18. The non-transitory computer-readable storage medium of claim 16, wherein one or more of the header networks are configured to operate concurrently.
19. 19. The non-transitory computer-readable storage medium of claim 16, wherein the deep neural network is configured to change between the plurality of head networks during the inspection.
20. 20. The non-transitory computer-readable storage medium of claim 16, wherein the workpiece is a semiconductor wafer.

Description

Semiconductor inspection system with deep neural network Cross reference to related applications The present application claims priority to provisional patent application No. 63/607,106, U.S. application No. 2023, 12, 7, the contents of which are hereby incorporated by reference. Technical Field The present disclosure relates to semiconductor inspection. Background The evolution of the semiconductor manufacturing industry places higher demands on yield management and in particular on metrology and inspection systems. Critical dimensions continue to shrink, but the industry needs to reduce the time to achieve high yield, high value production. Minimizing the total time from detection of a yield problem to resolution of the problem determines the return on investment for the semiconductor manufacturer. Manufacturing semiconductor devices, such as logic and memory devices, typically involves processing workpieces, such as semiconductor wafers, using a large number of manufacturing processes to form various features and multiple levels of the semiconductor devices. For example, photolithography is a semiconductor manufacturing process that involves transferring a pattern from a reticle to a photoresist disposed on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical Mechanical Polishing (CMP), etching, deposition, and ion implantation. An arrangement of multiple semiconductor devices fabricated on a single semiconductor wafer may be separated into individual semiconductor devices. Inspection processes are used at various steps during semiconductor manufacturing to detect defects on wafers to facilitate higher yields in the manufacturing process and thus higher profits. Verification has been an important part of the manufacture of semiconductor devices, such as Integrated Circuits (ICs). However, as semiconductor devices decrease in size, inspection becomes more important for successful manufacture of acceptable semiconductor devices because smaller defects may cause the device to fail. For example, as the size of semiconductor devices is reduced, detection of reduced-size defects becomes necessary because even relatively small defects can cause unwanted aberrations in the semiconductor devices. However, as design rules shrink, semiconductor manufacturing processes may operate closer to the limitations of the process' performance capabilities. In addition, as design rules shrink, smaller defects may have an impact on the electrical parameters of the device, which drives more sensitive inspection. As design rules shrink, the population of potential yield-related defects detected by inspection increases dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Thus, more defects can be detected on the wafer, and it can be difficult and expensive to correct the process to eliminate all defects. Determining which defects actually affect the electrical parameters and yield of the device may allow the process control method to focus on the defects while largely ignoring other defects. Furthermore, under smaller design rules, in some cases, process-induced failures tend to be systematic. That is, process-induced failures tend to fail in a predetermined design pattern that is typically repeated multiple times within the design. Eliminating spatially systematic, electrically related defects can have an impact on yield. Deep Neural Networks (DNNs) may be used to identify and classify defects in inspection images, but DNNs have limitations. Previously, image-based DNNs operated by saving the model into a binary file, such as TensorFlow or Torch, that is ready for inference. At inference time, the binary model is loaded into the CPU or GPU memory using a dedicated c++ library or using Python. If the model does not fit to the available GPU memory, the model is not loaded into memory. For example, the 20 GB model cannot be fitted to a 12 GB GPU device. Loading the model into memory can take a few seconds because the GPU device needs to allocate hundreds of unified compute architecture (CUDA) buffers and load a large amount of network weights into memory. After loading, the model may be used. However, if different inspection tasks require different models, then the models need to be removed and new models loaded in their place. This unload and load process takes time, which slows down the inspection throughput. New systems and techniques are needed. Disclosure of Invention In a first embodiment, a system is provided. The system includes a light source that generates a light beam, a stage configured to hold a workpiece (e.g., a semiconductor wafer) in a path of the light beam, a detector that receives the light beam reflected from the workpiece, a processor (e.g., a CPU or GPU) in electronic communication with the detector, and an electronic data storage unit in electronic communication with the processor. The p