CN-121986369-A - Shift register unit, display driving circuit and display device

Abstract

A shift register unit, a display driving circuit and a display device belong to the technical field of display. The shift register unit includes an input control circuit (01) and an output control circuit (02), wherein the input control circuit (01) is capable of controlling on-off of an input signal terminal (IN_n) and an input node (Q_n) based on a first clock signal supplied from a first clock line (CB), a second clock signal supplied from a second clock line (CKn), and the output control circuit (02) is capable of controlling the potential of an output signal terminal (OUT_n) based on the potential of the input node (Q_n), an enable signal supplied from an enable line (EN), and a reset control signal supplied from a reset line (Trst), so that the shift register unit can be caused to output signals matching P-type transistors and/or N-type transistors IN pixels by flexibly setting the enable signal, the clock signal, and the reset control signal. And because the output control circuit (02) and the input control circuit (01) are distributed along the first direction (X1) and along the direction close to the pixels, signal lines connected with the output control circuit (02) and the input control circuit (01) extend along the second direction (Y1) intersecting the first direction (X1), and the narrow frame design of the display device can be facilitated.

Inventors

• LU JIANGNAN
• SHANG GUANGLIANG
• ZHAO XULIANG
• CUI SONG
• ZHU JIANCHAO
• FENG YU
• LIU LIBIN
• FENG KE
• XIAN JIANBO

Assignees

• 京东方科技集团股份有限公司

Dates

Publication Date

20260505

Application Date

20240827

Claims (20)

1. A shift register unit, the shift register unit comprising: The input control circuit is respectively connected with the first clock line, the second clock line, the input signal end and the input node and is used for responding to the first clock signal provided by the first clock line and the second clock signal provided by the second clock line to control the on-off of the input signal end and the input node; The output control circuit is respectively connected with the input node, the reset control line, the enabling line and the output signal end and is used for controlling the potential of the output signal end based on the potential of the input node, the enabling signal provided by the enabling line and the reset control signal provided by the reset control line; the output control circuit and the input control circuit are arranged along a first direction and along a direction close to the pixel; The reset control line, the first clock line, the second clock line and the enable line are arranged along the first direction, along a direction close to the pixel and extend along a second direction, wherein the second direction intersects with the first direction.
2. The shift register unit according to claim 1, wherein the output control circuit includes: A first output control sub-circuit connected to the input node, the reset control line, and a first intermediate node, respectively, and configured to control a potential of the first intermediate node based on a potential of the input node and the reset control signal; a second output control sub-circuit connected to the first intermediate node and the second intermediate node, respectively, and configured to control a potential of the second intermediate node based on the potential of the first intermediate node; A third output control sub-circuit connected to the second intermediate node, the enable line, and the output signal terminal, respectively, and configured to control the potential of the output signal terminal based on the potential of the second intermediate node and the enable signal; And, the first output control sub-circuit and the input control circuit in the output control circuit are arranged along the first direction and along a direction approaching the pixel; the first output control sub-circuit, the second output control sub-circuit and the third output control sub-circuit are arranged along the first direction and along the direction close to the pixel, and the second output control sub-circuit and the input control circuit are arranged along the second direction.
3. The shift register unit of claim 2, wherein the shift register unit further comprises: the latch circuit is respectively connected with a third clock line, a fourth clock line, the second intermediate node and the input node and is used for responding to a third clock signal provided by the third clock line and a fourth clock signal provided by the fourth clock line to control the on-off of the second intermediate node and the input node, and the potential of the second intermediate node is opposite to that of the first intermediate node; The switch control circuit is connected between the enabling line and the third output control sub-circuit, is also respectively connected with a first control end and a second control end, and is used for responding to a first control signal provided by the first control end and a second control signal provided by the second control end to control the on-off of the enabling line and the third output control sub-circuit; The drive enhancement circuit is connected between the third output control sub-circuit and the output signal end and is used for outputting the potential of the output signal of the third output control sub-circuit to the output signal end after at least one inversion treatment; The latch circuit, the switch control circuit and the drive enhancing circuit are arranged along the first direction and along a direction close to the pixel, and the latch circuit and the input control circuit are arranged along the second direction and between the input control circuit and the second output control sub-circuit; The third clock line and the fourth clock line are located between the reset control line and the enable line, are arranged in the first direction and in a direction close to the pixel, and extend in the second direction.
4. The shift register unit of claim 3, wherein the input control circuit comprises a first transmission gate, the first output control sub-circuit comprises a first nor gate, the second output control sub-circuit comprises a first nor gate, the third output control sub-circuit comprises a second nor gate, the latch circuit comprises a second transmission gate, the switch control circuit comprises a third transmission gate, the drive enhancement circuit comprises a second nor gate, a third nor gate and a fourth nor gate connected in series in sequence; The first transmission gate is connected between the input signal end and the input node and is also connected with the first clock line and the second clock line respectively, two input ends of the first nor gate are respectively connected with the reset control line and the input node, the output end of the first nor gate is connected with the first intermediate node, the input end of the first nor gate is connected with the first intermediate node, the output end of the first nor gate is connected with the second intermediate node, one input end of the second nor gate is connected with the second intermediate node, the other input end of the second nor gate is connected with the enable line through the third transmission gate, the third transmission gate is also respectively connected with the first control end and the second control end, the output end of the second nor gate is connected with the output signal end through the second nor gate, the third nor gate and the fourth nor gate which are sequentially connected in series, the second transmission gate is connected with the second intermediate node, the other input end of the second nor gate is connected with the second clock line, the second output end of the second nor gate is connected with the second clock line, and the second output end of the second output unit is connected with the second clock line; The first NOR gate comprises a first group of circuits of the first transmission gate, the second transmission gate and the first NOR gate, a second group of circuits of the second NOR gate and the third transmission gate comprises a third group of circuits of the second NOR gate and the voltage stabilizing capacitor, the third NOR gate and the fourth NOR gate are arranged along the first direction and along the direction close to the pixel, the first transmission gate, the second transmission gate and the first NOR gate are arranged along the second direction in the first group of circuits, the second NOR gate and the third transmission gate are arranged along the second direction in the second group of circuits, and the third transmission gate is far away from the first transmission gate relative to the second NOR gate, and the second NOR gate and the voltage stabilizing capacitor are arranged along the second direction and far away from the second NOR gate relative to the second NOR gate in the third group of circuits.
5. The shift register cell of claim 4, wherein the shift register cell is located on a substrate and along the second direction: The length of orthographic projection of at least two circuits of the first nor gate, the first group of circuits, the second group of circuits, the third nor gate and the fourth nor gate on the substrate is equal; and/or the length of orthographic projection of the second nor gate and the second nor gate on the substrate is equal; And/or lengths of orthographic projections of at least two circuits of the first transmission gate, the second transmission gate, the first NOT gate, the third transmission gate and the voltage stabilizing capacitor on the substrate are equal.
6. The shift register unit of claim 4 or 5, wherein the shift register unit is located on a substrate and along the first direction: In the first group of circuits, the widths of orthographic projections of at least two circuits of the first transmission gate, the second transmission gate and the first NOT gate on the substrate are equal; And/or, in the second set of circuits, the width of orthographic projection of the second nor gate and the third transmission gate on the substrate is equal; and/or in the third group of circuits, the width of orthographic projection of the second NOT gate and the stabilizing capacitor on the substrate is equal.
7. The shift register cell of any of claims 4-6, wherein the first nor gate, the second nor gate, and the third nor gate are coupled to a first set of power lines and are configured to operate based on power signals provided by the first set of power lines; Wherein, any one of the first group of power lines and the second group of power lines comprises a first power line and a second power line which have different potentials of the provided power signals; The first power line and the second power line included in the first group of power lines are at least located on two sides of at least one signal line in the enabling line and the reset control line in the first direction, and the first power line and the second power line included in any group of power lines extend along the second direction; And the width of the first power line included in the second group of power lines is larger than the width of the first power line included in the first group of power lines, and the width of the second power line included in the second group of power lines is larger than the width of the second power line included in the first group of power lines.
8. The shift register unit according to claim 7, wherein at least adjacent three signal lines among the first clock line, the second clock line, the third clock line, the fourth clock line, the enable line, the reset control line, and the first and second power lines included in any one of the sets of power lines are arranged at equal intervals in the first direction.
9. The shift register cell of any of claims 4-8, wherein the first transmission gate comprises a first P-type transistor and a first N-type transistor; The grid electrode of the first P-type transistor and the grid electrode of the first N-type transistor are respectively connected with the first clock line and the second clock line, the first pole of the first P-type transistor and the first pole of the first N-type transistor are both connected with the input signal end, and the second pole of the first P-type transistor and the second pole of the first N-type transistor are both connected with the input node; and the first P-type transistor and the first N-type transistor are arranged along the first direction and along a direction close to the second nor gate.
10. The shift register cell of any of claims 4-9, wherein the first nor gate comprises a second P-type transistor, a second N-type transistor, a third P-type transistor, and a third N-type transistor; The grid electrode of the second P-type transistor and the grid electrode of the third N-type transistor are connected with the reset control line, the first electrode of the second P-type transistor is connected with the first power line, the second electrode of the second P-type transistor is connected with the first electrode of the third P-type transistor, the second electrode of the second N-type transistor and the second electrode of the third N-type transistor are connected with the first intermediate node, the first electrode of the second N-type transistor and the first electrode of the third N-type transistor are connected with the second power line, and the grid electrode of the third P-type transistor and the grid electrode of the second N-type transistor are connected with the input node; The third P-type transistor and the second P-type transistor are arranged in series along the second direction, the second N-type transistor is located at one side, far away from the second P-type transistor, of the third P-type transistor, the second N-type transistor is close to the first transmission gate relative to the third P-type transistor, the third N-type transistor is located at one side, far away from the third P-type transistor, of the second P-type transistor, and the third N-type transistor is close to the first NOT gate relative to the second P-type transistor.
11. The shift register cell of any one of claims 4 to 10, wherein the first NOT gate comprises a fourth P-type transistor and a fourth N-type transistor, and the fourth N-type transistor is a double gate transistor; The grid electrode of the fourth P-type transistor and the grid electrode of the fourth N-type transistor are connected with the first intermediate node, the first pole of the fourth P-type transistor and the first pole of the fourth N-type transistor are respectively connected with the first power line and the second power line, and the second pole of the fourth P-type transistor and the second pole of the fourth N-type transistor are connected with the second intermediate node; and the fourth N-type transistor and the fourth P-type transistor are arranged along the first direction and along a direction approaching the third transfer gate.
12. The shift register cell of any of claims 4-11, wherein the second transfer gate comprises a fifth P-type transistor and a fifth N-type transistor; the grid electrode of the fifth P-type transistor and the grid electrode of the fifth N-type transistor are respectively connected with the third clock line and the fourth clock line, the first pole of the fifth P-type transistor and the first pole of the fifth N-type transistor are both connected with the first intermediate node, and the second pole of the fifth P-type transistor and the second pole of the fifth N-type transistor are both connected with the input node; And the fifth P-type transistor and the fifth N-type transistor are arranged along the first direction and along a direction approaching the second nor gate.
13. The shift register cell of any of claims 4-12, wherein the third transfer gate comprises a sixth P-type transistor and a sixth N-type transistor; The grid electrode of the sixth P-type transistor and the grid electrode of the sixth N-type transistor are respectively connected with the first control end and the second control end, the first pole of the sixth P-type transistor and the first pole of the sixth N-type transistor are both connected with the enabling line, and the second pole of the sixth P-type transistor and the second pole of the sixth N-type transistor are both connected with the other input end of the second NOR gate; and the sixth N-type transistor and the sixth P-type transistor are arranged along the first direction and along a direction close to the voltage stabilizing capacitor.
14. The shift register cell of any of claims 4 to 13, wherein the second nor gate comprises a seventh P-type transistor, a seventh N-type transistor, an eighth P-type transistor, and an eighth N-type transistor; The gate of the seventh P-type transistor and the gate of the eighth N-type transistor are both connected with the third transmission gate, the gate of the eighth P-type transistor and the gate of the seventh N-type transistor are both connected with the second intermediate node, the first pole of the seventh P-type transistor is connected with a first power line, the second pole of the seventh P-type transistor is connected with the first pole of the eighth P-type transistor, the second pole of the seventh N-type transistor and the second pole of the eighth N-type transistor are both connected with the input end of the second NOT gate, and the first pole of the seventh N-type transistor and the first pole of the eighth N-type transistor are both connected with a second power line; And the eighth P-type transistor and the seventh N-type transistor are arranged in the second direction and in a direction close to the third transfer gate, the seventh P-type transistor and the eighth N-type transistor are arranged in the second direction and in a direction close to the third transfer gate, the seventh N-type transistor and the eighth N-type transistor are arranged in the first direction and in a direction close to the second not gate, and the eighth P-type transistor and the seventh P-type transistor are arranged in the first direction and in a direction close to the second not gate.
15. The shift register cell of any one of claims 4 to 14, wherein the second NOT gate comprises a ninth P-type transistor and a ninth N-type transistor, wherein the third NOT gate comprises a tenth P-type transistor and a tenth N-type transistor, and wherein the fourth NOT gate comprises an eleventh P-type transistor and an eleventh N-type transistor; the grid electrode of the ninth P-type transistor and the grid electrode of the ninth N-type transistor are both connected with the output end of the second NOR gate, the grid electrode of the tenth P-type transistor and the grid electrode of the tenth N-type transistor are both connected with the second pole of the ninth P-type transistor and the second pole of the ninth N-type transistor, the grid electrode of the eleventh P-type transistor and the grid electrode of the eleventh N-type transistor are both connected with the second pole of the tenth P-type transistor and the second pole of the tenth N-type transistor, the second pole of the eleventh P-type transistor and the second pole of the eleventh N-type transistor are both connected with the output signal end, the first pole of the ninth P-type transistor, the first pole of the tenth P-type transistor and the first pole of the eleventh P-type transistor are both connected with a first power line, and the first pole of the ninth N-type transistor and the first pole of the eleventh N-type transistor are both connected with a second power line; The ninth P-type transistor and the ninth N-type transistor are arranged along the second direction and along a direction close to the voltage stabilizing capacitor, the tenth P-type transistor and the tenth N-type transistor are arranged along the second direction, the tenth N-type transistor is close to the voltage stabilizing capacitor relative to the tenth P-type transistor, the eleventh P-type transistor and the eleventh N-type transistor are arranged along the first direction and along a direction close to the pixel, or the eleventh P-type transistor and the eleventh N-type transistor are arranged along the second direction, and the eleventh N-type transistor is close to the voltage stabilizing capacitor relative to the eleventh P-type transistor.
16. The shift register unit according to any one of claims 4 to 15, wherein a size of a transistor included in the second nor gate, the third nor gate, and the fourth nor gate sequentially increases, and a size of a transistor included in the second nor gate is larger than a size of a transistor included in at least one circuit of the first nor gate, the first transfer gate, the second transfer gate, the first nor gate, the second nor gate, and the third transfer gate.
17. The shift register cell according to any one of claims 1 to 16, wherein the transistor in the shift register cell includes a first active layer, a first gate metal layer, a second active layer, a first source drain metal layer, and a second source drain metal layer on one side of the substrate, the first active layer serving as an active layer of a P-type transistor in the shift register cell, and the second active layer serving as an active layer of an N-type transistor in the shift register cell; In addition, when the material of the first active layer is different from the material of the second active layer, the first active layer and the second active layer are located in different layers, and the first active layer, the first gate metal layer, the second active layer, the first source drain metal layer, and the second source drain metal layer are sequentially stacked in a direction away from the substrate; and under the condition that the material of the first active layer is the same as that of the second active layer, the first active layer and the second active layer are positioned on the same layer and are sequentially laminated with the first gate metal layer, the second active layer, the first source drain metal layer and the second source drain metal layer along the direction away from the substrate.
18. The shift register cell of claim 17, wherein at least a portion of the first source drain metal layer is multiplexed with at least one of the first active layer, the first gate metal layer, and the second active layer to reduce an overlapping area of the first source drain metal layer and the second source drain metal layer.
19. A display driving circuit comprising a plurality of shift register units as claimed in any one of claims 1 to 18 in cascade.
20. A display device comprising a display panel, and the display driving circuit according to claim 19; The display panel comprises a plurality of pixels which are arranged in an array, and the display driving circuit is connected with the pixels and is used for transmitting display driving signals to the pixels so as to drive the pixels to emit light.

Description

Shift register unit, display driving circuit and display device Technical Field The present application relates to the field of display technologies, and in particular, to a shift register unit, a display driving circuit, and a display device. Background With the development of display technology, an array substrate row driving (GATE DRIVER on array, GOA) technology may be used to integrate display driving circuits such as a gate driving circuit and a light emitting driving circuit on a display panel, so as to facilitate the design of a narrow frame of the display panel. Accordingly, the display driving circuit is also referred to as a GOA circuit. Currently, GOA circuits generally include a plurality of shift register cells (also referred to as GOA cells) in cascade. Each GOA unit generally includes a plurality of transistors connected to a plurality of signal lines and pixels on a display panel, respectively, and configured to output a desired display driving signal to the pixels based on signals supplied from the plurality of signal lines to drive the pixels to emit light. However, the structure of the current GOA unit is complex, the number of connected signal lines is large, and the narrow frame design of the display panel cannot be better facilitated. Disclosure of Invention A shift register unit, a display driving circuit, and a display device are provided. The technical scheme is as follows: in one aspect, there is provided a shift register unit including: The input control circuit is respectively connected with the first clock line, the second clock line, the input signal end and the input node and is used for responding to the first clock signal provided by the first clock line and the second clock signal provided by the second clock line to control the on-off of the input signal end and the input node; The output control circuit is respectively connected with the input node, the reset control line, the enabling line and the output signal end and is used for controlling the potential of the output signal end based on the potential of the input node, the enabling signal provided by the enabling line and the reset control signal provided by the reset control line; the output control circuit and the input control circuit are arranged along a first direction and along a direction close to the pixel; The reset control line, the first clock line, the second clock line and the enable line are arranged along the first direction, along a direction close to the pixel and extend along a second direction, wherein the second direction intersects with the first direction. Optionally, the output control circuit includes: A first output control sub-circuit connected to the input node, the reset control line, and a first intermediate node, respectively, and configured to control a potential of the first intermediate node based on a potential of the input node and the reset control signal; a second output control sub-circuit connected to the first intermediate node and the second intermediate node, respectively, and configured to control a potential of the second intermediate node based on the potential of the first intermediate node; A third output control sub-circuit connected to the second intermediate node, the enable line, and the output signal terminal, respectively, and configured to control the potential of the output signal terminal based on the potential of the second intermediate node and the enable signal; And, the first output control sub-circuit and the input control circuit in the output control circuit are arranged along the first direction and along a direction approaching the pixel; the first output control sub-circuit, the second output control sub-circuit and the third output control sub-circuit are arranged along the first direction and along the direction close to the pixel, and the second output control sub-circuit and the input control circuit are arranged along the second direction. Optionally, the shift register unit further includes: the latch circuit is respectively connected with a third clock line, a fourth clock line, the second intermediate node and the input node and is used for responding to a third clock signal provided by the third clock line and a fourth clock signal provided by the fourth clock line to control the on-off of the second intermediate node and the input node, and the potential of the second intermediate node is opposite to that of the first intermediate node; The switch control circuit is connected between the enabling line and the third output control sub-circuit, is also respectively connected with a first control end and a second control end, and is used for responding to a first control signal provided by the first control end and a second control signal provided by the second control end to control the on-off of the enabling line and the third output control sub-circuit; The drive enhancement circuit is connected between the third output control sub-circuit an