CN-121986371-A - Source electrode driving circuit, display panel, display device and driving method

CN121986371ACN 121986371 ACN121986371 ACN 121986371ACN-121986371-A

Abstract

A source driving circuit, a display panel, a display device and a driving method thereof comprise a first input sub-circuit (301), a second input sub-circuit (302), a node control sub-circuit (303) and an output sub-circuit (304), wherein the first input sub-circuit (301) comprises a first input sub-unit (3011), a second input sub-unit (3012) and a third input sub-unit (3013), the first input sub-unit (3011) provides a scanning start signal for the first node (N1), a signal of a first reference signal end (VGH) for the second node (N2), the second input sub-unit (3012) provides a signal of the first reference signal end (VGH) for the second node (N2), the third input sub-unit (3013) provides a signal of a third control signal end (SW 3) for the second node (N2), and the second input sub-circuit (302) provides a signal of the second control signal end (SW 2) for the third node (N3), so that partial refreshing of a part of a column in the display panel can be realized, and power consumption can be saved.

Inventors

YU ZIYANG
ZHENG HAI
HUANG YINGLONG
ZHAO GUOWEI
CHEN DU
ZHAO TINGTING

Assignees

京东方科技集团股份有限公司
成都京东方光电科技有限公司

Dates

Publication Date: 20260505
Application Date: 20250623
Priority Date: 20240830

Claims (20)

The source electrode driving circuit comprises a first input sub-circuit, a second input sub-circuit, a node control sub-circuit and an output sub-circuit, wherein the first input sub-circuit comprises a first input sub-unit, a second input sub-unit and a third input sub-unit; The first input subunit is configured to respond to an effective voltage signal in signals of a first control signal end, provide a scanning start signal in signals of a data signal end to a first node, and provide signals of a first reference signal end to a second node, wherein the signals of the first control signal end comprise one effective voltage signal in one frame of display time, and the signals of the data signal end comprise a scanning start signal and a data voltage signal which appear in sequence; the second input subunit is configured to respond to the signal of the pull-up node and the signal of the second control signal end and provide the signal of the first reference signal end to the second node; The third input subunit is configured to respond to the signal of the first node and provide the signal of a third control signal end to the second node; The second input subcircuit is configured to provide a signal of a second control signal terminal to a third node in response to a signal of the first clock signal terminal; The node control subcircuit is configured to control signals of a pull-up node and a pull-down node according to signals of the second node and the third node; The output sub-circuit is configured to provide a signal of the first reference signal terminal to a drive output terminal in response to a signal of the pull-up node, and to provide a signal of the second reference signal terminal to the drive output terminal in response to a signal of the pull-down node.
The source driving circuit of claim 1, wherein the first input subunit comprises a first transistor and a second transistor; The control end of the first transistor is coupled with the first control signal end, the first end of the first transistor is coupled with the data signal end, and the second end of the first transistor is coupled with the first node; The control terminal of the second transistor is coupled to the first control signal terminal, the first terminal of the second transistor is coupled to the first reference signal terminal, and the second terminal of the second transistor is coupled to the second node.
The source driving circuit of claim 1, wherein the second input subunit comprises a third transistor, a fourth transistor, and a fifth transistor; The control end of the third transistor is coupled with the second control signal end, the first end of the third transistor is coupled with the second end of the fifth transistor, and the second end of the third transistor is coupled with the first node; The control end of the fourth transistor is coupled with the second control signal end, the first end of the fourth transistor is coupled with the second end of the fifth transistor, and the second end of the fourth transistor is coupled with the second node; the control terminal of the fifth transistor is coupled to the pull-up node, and the first terminal of the fifth transistor is coupled to the first reference signal terminal.
The source driving circuit of claim 1, wherein the third input subunit comprises a sixth transistor; the control terminal of the sixth transistor is coupled to the first node, the first terminal of the sixth transistor is coupled to the third control signal terminal, and the second terminal of the sixth transistor is coupled to the second node.
The source driving circuit of claim 4, wherein the third input subunit further comprises a first capacitor; The first end of the first capacitor is coupled to the first node, and the second end of the first capacitor is coupled to the second node.
The source driving circuit of claim 1, wherein the node control sub-circuit comprises a first control sub-unit, a second control sub-unit, and a third control sub-unit; The first control subunit is coupled with the second node, a sixth node, the second reference signal terminal and the pull-down node, the first control subunit is configured to provide the signal of the second node to the pull-down node in response to the signal of the second reference signal terminal, and to provide the signal of the second node to the sixth node in response to the signal of the second reference signal terminal, and to provide the signal of the sixth node to the pull-down node in response to the signal of the sixth node; The second control subunit is coupled to the second node, the third node, a first reference signal terminal, the first clock signal terminal, a second clock signal terminal, and the sixth node, the second control subunit being configured to provide the signal of the first clock signal terminal to the third node in response to the signal of the second node; providing the signal of the first reference signal terminal to a seventh node in response to the signal of the third node, and providing the signal of the second clock signal terminal to the seventh node in response to the signal of the sixth node; The third control subunit is coupled to the second node, the third node, the second reference signal terminal, the second clock signal terminal, the first reference signal terminal, and the pull-up node, and is configured to provide the signal of the second clock signal terminal to the pull-up node in response to the signals of the second reference signal terminal, the third node, and the second clock signal terminal, and to provide the signal of the first reference signal terminal to the pull-up node in response to the signal of the second node.
The source driving circuit of claim 6, wherein the first control subunit comprises an eighth transistor, a ninth transistor, and a tenth transistor; The control end of the eighth transistor is coupled with a second reference signal end, the first end of the eighth transistor is coupled with the second node, and the second end of the eighth transistor is coupled with the pull-down node; a control terminal of the ninth transistor is coupled to the second reference signal terminal, a first terminal of the ninth transistor is coupled to the second node, and a second terminal of the ninth transistor is coupled to a sixth node; The control terminal of the tenth transistor is coupled to the sixth node, the first terminal of the tenth transistor is coupled to the sixth node, and the second terminal of the tenth transistor is coupled to the pull-down node.
The source driving circuit of claim 6, wherein the second control subunit comprises an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a second capacitance; A control terminal of the eleventh transistor is coupled to the second node, a first terminal of the eleventh transistor is coupled to the first clock signal terminal, and a second terminal of the eleventh transistor is coupled to the third node; A control terminal of the twelfth transistor is coupled to the third node, a first terminal of the twelfth transistor is coupled to the seventh node, and a second terminal of the twelfth transistor is coupled to a first reference signal terminal; A control terminal of the thirteenth transistor is coupled to the sixth node, a first terminal of the thirteenth transistor is coupled to the second clock signal terminal, and a second terminal of the thirteenth transistor is coupled to a seventh node; The first end of the second capacitor is coupled with the sixth node, and the second end of the second capacitor is coupled with the seventh node.
The source driving circuit of claim 6, wherein the third control subunit comprises a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, and a third capacitor; A control terminal of the fourteenth transistor is coupled to the second reference voltage signal terminal, a first terminal of the fourteenth transistor is coupled to the third node, and a second terminal of the fourteenth transistor is coupled to the first terminal of the third capacitor; A control terminal of the fifteenth transistor is coupled to the first terminal of the third capacitor, the first terminal of the fifteenth transistor is coupled to the second terminal of the third capacitor, and the second terminal of the fifteenth transistor is coupled to the second clock signal terminal; A control terminal of the sixteenth transistor is coupled to the second clock signal terminal, a first terminal of the sixteenth transistor is coupled to the second terminal of the third capacitor, and a second terminal of the sixteenth transistor is coupled to the pull-up node; The control terminal of the seventeenth transistor is coupled to the second node, the first terminal of the seventeenth transistor is coupled to the first reference signal terminal, and the second terminal of the seventeenth transistor is coupled to the pull-up node.
The source driving circuit according to any one of claims 1 to 9, wherein the output sub-circuit includes an eighteenth transistor, a fourth capacitor, and a nineteenth transistor; A control terminal of the eighteenth transistor is coupled to the pull-down node, a first terminal of the eighteenth transistor is coupled to the second reference signal terminal, and a second terminal of the eighteenth transistor is coupled to the drive output terminal; the first end of the fourth capacitor is coupled with the pull-up node, and the second end of the fourth capacitor is coupled with the first reference signal end; A control terminal of the nineteenth transistor is coupled to the pull-up node, a first terminal of the nineteenth transistor is coupled to the drive output terminal, and a second terminal of the nineteenth transistor is coupled to the first reference signal terminal.
The source drive circuit according to any one of claims 6 to 9, further comprising a first pull-down control subcircuit; The first pull-down control subcircuit is configured to provide a signal of the second reference signal terminal to the sixth node in response to at least one of the drive output terminal, the pull-down node, the first node, or the signal of the second node.
The source driver circuit of claim 11, wherein the first pull-down control subcircuit comprises a twentieth transistor; the control terminal of the twentieth transistor is coupled to at least one of the drive output terminal, the pull-down node, the first node, or the second node, the first terminal of the twentieth transistor is coupled to the second reference signal terminal, and the second terminal of the twentieth transistor is coupled to the sixth node.
The source driver circuit of claim 11, further comprising a second pull-down control sub-circuit; The first pull-down control subcircuit is coupled to the second reference signal terminal via the second pull-down control subcircuit, the second pull-down control subcircuit being configured to provide a signal of the second reference signal terminal to the first pull-down control subcircuit in response to a signal of the drive output terminal.
The source driver circuit of claim 13, wherein the second pull-down control sub-circuit comprises a twenty-first transistor; The control terminal of the twenty-first transistor is coupled to the drive output terminal, the first terminal of the twenty-first transistor is coupled to the first pull-down control subcircuit, and the second terminal of the twenty-first transistor is coupled to the second reference signal terminal.
The source drive circuit according to any one of claims 1 to 14, further comprising a reset sub-circuit; The reset sub-circuit is configured to provide a signal of a first reference signal terminal to the second node in response to a signal of a node control signal terminal.
The source driver circuit of claim 15, wherein the reset sub-circuit comprises a twenty-second transistor; The control end of the twenty-second transistor is coupled with the node control signal end, the first end of the twenty-second transistor is coupled with the second node, and the second end of the twenty-second transistor is coupled with the first reference signal end.
The source drive circuit according to any one of claims 1 to 16, wherein the second reference signal terminal includes a first sub-reference signal terminal and a second sub-reference signal terminal; The first reference signal terminal comprises a first reference sub-signal terminal and a second reference sub-signal terminal.
The source driving circuit of claim 17, wherein a magnitude of the voltage value of the first sub-reference signal terminal is greater than or equal to a magnitude of the voltage value of the second sub-reference signal terminal.
The source driving circuit of claim 17, wherein a magnitude of the voltage value of the second reference sub-signal terminal is greater than or equal to a magnitude of the voltage value of the first reference sub-signal terminal.
A display panel, comprising: The display area comprises a plurality of sub-pixels, a plurality of column refreshing lines and a plurality of data lines, wherein each sub-pixel comprises a light emitting device and a pixel driving circuit connected with the light emitting device, one column refreshing line is connected with the pixel driving circuit of at least part of sub-pixels in one column of sub-pixels, and one data line is connected with the pixel driving circuit of at least part of sub-pixels in one column of sub-pixels; A non-display region including a plurality of source control lines including a first source control line and a second source control line, or including the first source control line, the second source control line, and a third source control line, and a plurality of source driving circuits according to any one of claims 1 to 19, a driving output terminal of one of the plurality of source driving circuits being connected to the column refresh line of the plurality of column refresh lines, a data signal terminal of one of the plurality of source driving circuits being connected to the data line of the plurality of data lines, a first control signal terminal of one of the plurality of source driving circuits being connected to the first source control line of the plurality of source control lines, a second control signal terminal of one of the plurality of source driving circuits being connected to the second control line of the plurality of source control lines, and a second control signal terminal of one of the plurality of source driving circuits being connected to the source control line of the plurality of source control lines.

Description

Source electrode driving circuit, display panel, display device and driving method The application claims priority from PCT patent application filed at month 8 and 30 of 2024, application number PCT/CN2024/115895 entitled "source driver circuit, display panel, display device, and driving method", the contents of which are understood to be incorporated herein by reference. Technical Field The present disclosure relates to the field of display technologies, and in particular, to a source driving circuit, a display panel, a display device and a driving method. Background Currently, when updating a screen, a conventional display panel needs to initialize and write data voltages of all pixels in one frame. In some special pictures (such as static pictures, pictures with less updating, pictures with only updating of a certain column, etc.), the data voltage of most pixels in the whole screen can be maintained at the original display brightness through the low-leakage transistor without updating, and the repeated brushing of the pixels causes a waste of a part of power consumption. Disclosure of Invention The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims. The embodiment of the disclosure provides a source electrode driving circuit, a display panel, a display device and a driving method, which are used for reducing power consumption of the display panel in a display process. In one aspect, the embodiment of the disclosure provides a source driving circuit, which comprises a first input sub-circuit, a second input sub-circuit, a node control sub-circuit and an output sub-circuit, wherein the first input sub-circuit comprises a first input sub-unit, a second input sub-unit and a third input sub-unit; The first input subunit is configured to respond to an effective voltage signal in signals of a first control signal end, provide a scanning start signal in signals of a data signal end to a first node, and provide signals of a first reference signal end to a second node, wherein the signals of the first control signal end comprise one effective voltage signal in one frame of display time, and the signals of the data signal end comprise a scanning start signal and a data voltage signal which appear in sequence; the second input subunit is configured to respond to the signal of the pull-up node and the signal of the second control signal end and provide the signal of the first reference signal end to the second node; The third input subunit is configured to respond to the signal of the first node and provide the signal of a third control signal end to the second node; The second input subcircuit is configured to provide a signal of a second control signal terminal to a third node in response to a signal of the first clock signal terminal; The node control subcircuit is configured to control signals of a pull-up node and a pull-down node according to signals of the second node and the third node; The output sub-circuit is configured to provide a signal of the first reference signal terminal to a drive output terminal in response to a signal of the pull-up node, and to provide a signal of the second reference signal terminal to the drive output terminal in response to a signal of the pull-down node. In another aspect, an embodiment of the present disclosure further provides a display panel, including: The display area comprises a plurality of sub-pixels, a plurality of column refreshing lines and a plurality of data lines, wherein each sub-pixel comprises a light emitting device and a pixel driving circuit connected with the light emitting device, one column refreshing line is connected with the pixel driving circuit of at least part of sub-pixels in one column of sub-pixels, and one data line is connected with the pixel driving circuit of at least part of sub-pixels in one column of sub-pixels; a non-display area including a plurality of source control lines and a plurality of source driving circuits according to any one of the embodiments of the present disclosure, wherein the plurality of source control lines includes a first source control line and a second source control line, or includes the first source control line, the second source control line, and a third source control line, a driving output terminal of one of the plurality of source driving circuits is connected to one of the column refresh lines, a data signal terminal of one of the plurality of source driving circuits is connected to one of the data lines, a first control signal terminal of one of the plurality of source driving circuits is connected to one of the first source control lines, a second control signal terminal of one of the plurality of source driving circuits is connected to one of the second control lines, and a first control signal terminal of one of the plurality of source driving circuits is connected to one of the source control lines. In another aspe