CN-121986372-A - Display panel and display device

CN121986372ACN 121986372 ACN121986372 ACN 121986372ACN-121986372-A

Abstract

A display panel is divided into N areas (Z1-ZN), wherein any area comprises a display area (AA) and a peripheral area (BA), the display panel comprises N pixel subarrays, N grid driving circuits, N frame starting signal lines, (N-1) auxiliary grid driving circuits (G ') and an auxiliary grid driving circuit (G ') comprise at least one stage of auxiliary shift register (31), a first frame starting signal line (STV 1) is connected with a signal input end of a first stage shift register (21) of the first grid driving circuit (G1), when 2 is less than or equal to i and less than or equal to N, the i-th frame starting signal line is connected with a signal input end of a first stage auxiliary shift register (31) of the i-1 auxiliary grid driving circuit (G '), a signal output end of a last stage auxiliary shift register (31) of the i-1 auxiliary grid driving circuit (G ') is connected with a signal input end of a first stage shift register (21) of the i-1 auxiliary grid driving circuit, and when 2 is less than or equal to i, the i-1 auxiliary grid driving circuit (G ') comprises a signal input end of the first stage auxiliary shift register (31) of the adjacent auxiliary shift registers (31) in cascade connection.

Inventors

YANG HUIJUAN
MA HONGWEI
SHU XIAOQING
ZHANG SHUN
ZHANG YI
WEI LIHENG
HAN HONGDA
CHU ZHIWEN

Assignees

京东方科技集团股份有限公司
成都京东方光电科技有限公司

Dates

Publication Date: 20260505
Application Date: 20250624
Priority Date: 20240829

Claims (20)

A display panel divided into N areas sequentially arranged along a first direction, wherein any one of the areas comprises a display area and a peripheral area positioned on at least one side of the display area, N is an integer not less than 2; wherein, the display panel includes: the pixel subarray comprises a plurality of pixels which are arranged in rows and columns; For the grid driving circuits and the pixel subarrays which are positioned in the same area, the grid driving circuits are configured to respond to frame starting signals corresponding to the grid driving circuits and the pixel subarrays and provide grid driving signals for the pixel subarrays; n frame-on signal lines, each configured to supply the frame-on signal to the corresponding gate driving circuit, respectively; (N-1) auxiliary gate drive circuits comprising at least one stage of auxiliary shift registers; The frame starting signal line is connected with the signal input end of the first stage shift register of the first grid driving circuit, when i is more than or equal to 2 and less than or equal to N, the frame starting signal line is connected with the signal input end of the first stage auxiliary shift register of the i-1 auxiliary grid driving circuit, the signal output end of the last stage auxiliary shift register of the i-1 auxiliary grid driving circuit is connected with the signal input end of the first stage shift register of the i-1 auxiliary grid driving circuit, and when the auxiliary grid driving circuit comprises a multi-stage auxiliary shift register, two adjacent stages in the multi-stage auxiliary shift register are cascaded.
The display panel according to claim 1, wherein the ith auxiliary gate driving circuit is located in the (i+1) th peripheral region.
The display panel of claim 1, wherein at least a portion of the auxiliary gate drive circuit is located in a first one of the peripheral regions.
The display panel according to any one of claims 1 to 3, further comprising M redundant gate driving circuits, M being an integer not less than 1; At least part of the M redundant gate driving circuits are multiplexed as the auxiliary gate driving circuits.
The display panel of claim 4, wherein at least a portion of the M redundant gate drive circuits are located in a first one of the peripheral regions and correspond to corner regions of the first one of the display regions; For the auxiliary gate drive circuit located in the first of the peripheral regions, the auxiliary gate drive circuit is multiplexed by the redundant gate drive circuit located in the first of the peripheral regions.
The display panel of claim 5, wherein for the auxiliary gate drive circuit located in a first one of the peripheral regions, each of the auxiliary shift registers is located on a side of the first gate drive circuit facing away from a second one of the peripheral regions.
The display panel of claim 5, wherein for the auxiliary gate driving circuit located in a first one of the peripheral regions, each stage of the auxiliary shift register is located between stages of shift registers in the first gate driving circuit.
The display panel according to claim 1, wherein for part of the auxiliary gate driving circuits, the signal output terminals of part of the auxiliary shift registers are connected to compensation lines.
The display panel of claim 8, wherein the compensation line extends along the first direction and is located in the peripheral region.
The display panel according to claim 1, wherein the gate driving circuit includes at least a second reset driving circuit, a scan driving circuit, and a compensation driving circuit; the auxiliary gate driving circuit comprises a first auxiliary driving circuit, a second auxiliary driving circuit and a third auxiliary driving circuit; The first auxiliary driving circuit is correspondingly connected with the second reset driving circuit, the second auxiliary driving circuit is correspondingly connected with the scanning driving circuit, and the third auxiliary driving circuit is correspondingly connected with the compensation driving circuit.
The display panel of claim 10, wherein the gate driving circuit further comprises a first reset driving circuit, the pixel comprises a pixel driving circuit comprising a first reset transistor; the display panel further includes a plurality of first reset signal lines; The first reset signal line, the shift register corresponding to one stage of the first reset driving circuit and one row of pixels are arranged; for the corresponding first reset signal line, the shift register and the pixel, the control electrode of the first reset transistor is connected with the second end of the first reset signal line, and the first end of the first reset signal line is connected with the signal output end of the shift register.
The display panel of claim 11, wherein the display panel further comprises a plurality of first initial signal lines; A first pole of the first reset transistor is connected with the first initial signal line; the first reset transistors corresponding to the first stage shift registers in the 2 nd to N th gate driving circuits are called first type transistors, the first reset transistors corresponding to the other stages shift registers in the N gate driving circuits are called second type transistors, and the amplitude of the first initial signals transmitted by the first initial signal lines received by the first type transistors is different from the amplitude of the first initial signals transmitted by the first initial signal lines received by the second type transistors.
The display panel of claim 10, wherein the pixel comprises a pixel driving circuit comprising a second reset transistor and a third reset transistor; The display panel further includes a plurality of second reset signal lines; The second reset signal line, the shift register corresponding to one stage of the second reset driving circuit and one row of pixels are arranged; For the corresponding second reset signal line, the shift register and the pixel, the control electrodes of the second reset transistor and the third reset transistor are connected with the second end of the second reset signal line, and the first end of the second reset signal line is connected with the signal output end of the shift register.
The display panel of claim 13, wherein the display panel further comprises a plurality of second initial signal lines; A first pole of the second reset transistor is connected with the second initial signal line; The second reset transistors corresponding to the first stage shift registers in the 2 nd to N th gate driving circuits are called third type transistors, the second reset transistors corresponding to the other stages shift registers in the N gate driving circuits are called fourth type transistors, and the amplitude of the voltage signals transmitted by the second initial signal lines received by the third type transistors is different from the amplitude of the voltage signals transmitted by the second initial signal lines received by the fourth type transistors.
The display panel of claim 13, wherein the display panel further comprises a plurality of third initial signal lines; A first pole of the third reset transistor is connected with the third initial signal line; The third reset transistors corresponding to the first stage shift registers in the 2 nd to N th gate driving circuits are called fifth type transistors, the third reset transistors corresponding to the other stages shift registers in the N gate driving circuits are called sixth type transistors, and the amplitude of the voltage signals transmitted by the third initial signal lines received by the fifth type transistors is different from the amplitude of the voltage signals transmitted by the third initial signal lines received by the sixth type transistors.
The display panel of claim 10, wherein the pixel comprises a pixel drive circuit comprising a compensation transistor; The display panel further includes a plurality of first scan signal lines; The first scanning signal line, the shift register at one stage of the scanning driving circuit and one row of pixels are arranged correspondingly; For the corresponding first scanning signal line, the shift register and the pixel, the control electrode of the compensation transistor is connected with the second end of the first scanning signal line, and the first end of the first scanning signal line is connected with the signal output end of the shift register.
The display panel of claim 10, wherein the pixel comprises a pixel drive circuit comprising a data write transistor; the display panel further includes a plurality of second scan signal lines; the second scanning signal line, the shift register at one stage of the scanning driving circuit and one row of pixels are arranged correspondingly; For the corresponding second scanning signal line, the shift register and the pixel, the control electrode of the data writing transistor is connected with the second end of the second scanning signal line, and the first end of the second scanning signal line is connected with the signal output end of the shift register.
The display panel of claim 17, further comprising a plurality of data signal lines; The first pole of the data writing transistor is connected with one data signal line.
The display panel according to claim 10, wherein the gate driving circuit further comprises a light emission driving circuit, wherein the pixel comprises a pixel driving circuit comprising a light emission control transistor; the display panel further includes a plurality of light emission control signal lines; the light-emitting control signal line is arranged corresponding to the first-stage shift register of the light-emitting driving circuit and one row of pixels; For the corresponding light-emitting control signal line, the shift register and the pixel, the control electrode of the light-emitting control transistor is connected with the second end of the light-emitting control signal line, and the first end of the light-emitting control signal line is connected with the signal output end of the shift register.
A display device comprising the display panel of any one of claims 1-19.

Description

Display panel and display device Technical Field The present application relates to the field of display technologies, and in particular, to a display panel and a display device. Background With the rapid development of mobile products (e.g., mobile phones, smart tablets, etc.), various forms of products are appeared on the market, and among them, folded products are increasingly popular. For folded products, full-screen display is required when the folded products are not folded, partial display is required after the folding, and in order to save power consumption when the folded products are folded, GOAs (GATE DRIVER on Array, array substrate driving) are generally grouped by taking folding positions as boundaries. However, for a group-controlled folded product, a relatively significant difference is often formed at the fold when displayed full screen, such as a black line or a significant difference in brightness, etc., thereby forming a poor display. Disclosure of Invention In view of the above, the present application provides a display panel and a display device to solve or partially solve the above-mentioned problems. In view of the above object, in a first aspect, the present application provides a display panel divided into N regions sequentially arranged in a first direction, wherein any one of the regions includes a display region and a peripheral region located on at least one side of the display region, N is an integer not less than 2, the display panel includes N pixel sub-arrays each located in the N display regions, the pixel sub-arrays include a plurality of pixels arranged in rows and columns, N gate driving circuits each located in the N peripheral regions, the gate driving circuits are configured to provide a gate driving signal for the pixel sub-arrays in response to a frame on signal corresponding thereto for the gate driving circuits and the pixel sub-arrays located in the same region, the gate driving circuits include a shift register in cascade connection of a plurality of stages, the shift register corresponds to one of the pixels, N frame on signal lines each configured to provide the frame on signal for the gate driving circuits corresponding thereto, N-1) auxiliary gate driving circuits each including an auxiliary gate driving line, the auxiliary gate driving circuit includes at least one auxiliary gate driving line connected to the first stage i, the auxiliary gate driving circuit is connected to the first stage i signal input to the first stage i signal input to the first stage 1, the auxiliary gate driving circuit is connected to the first stage i signal input to the first stage 1, the first stage signal input to the first stage 1 is connected to the first stage 1, when the auxiliary gate driving circuit comprises a multi-stage auxiliary shift register, two adjacent stages in the multi-stage auxiliary shift register are cascaded. In some alternative embodiments, the ith auxiliary gate driving circuit is located in the (i+1) th peripheral region. In some alternative embodiments, at least a portion of the auxiliary gate drive circuit is located in a first of the peripheral regions. In some alternative embodiments, the method further comprises M redundant gate driving circuits, M is an integer not smaller than 1, and at least part of the redundant gate driving circuits in the M redundant gate driving circuits are multiplexed as the auxiliary gate driving circuits. In some alternative embodiments, at least a portion of the M redundant gate drive circuits are located in a first of the peripheral regions and correspond to corner regions of the first of the display regions, and for the auxiliary gate drive circuits located in the first of the peripheral regions, the auxiliary gate drive circuits are multiplexed by the redundant gate drive circuits located in the first of the peripheral regions. In some alternative embodiments, for the auxiliary gate driving circuit located in the first peripheral region, each stage of the auxiliary shift register is located on a side of the first stage of the first gate driving circuit facing away from the second peripheral region. In some alternative embodiments, for the auxiliary gate driving circuit located in the first peripheral region, each stage of the auxiliary shift register is located between stages of shift registers in the first gate driving circuit. In some alternative embodiments, for part of the auxiliary gate driving circuit, the signal output terminal of part of the auxiliary shift register is connected to the compensation line. In some alternative embodiments, the compensation line extends along the first direction and is located in the peripheral region. In some optional embodiments, the gate driving circuit at least comprises a second reset driving circuit, a scanning driving circuit and a compensation driving circuit, wherein the auxiliary gate driving circuit comprises a first auxiliary driving circuit, a second auxiliary drivi