CN-121986378-A - High-speed and area-efficient parallel read-write memory

Abstract

A memory is provided with a pair of banks including a first bank bit cell and a second bank bit cell. The I/O circuitry for the pair of banks includes a common write path configured to couple a write driver input signal to the first bank bit cell in response to assertion of a write enable signal for the first bank bit cell and to couple the write driver input signal to the second bank bit cell in response to assertion of a write enable signal for the second bank bit cell. The I/O circuit also includes a common read path configured to couple a data bit output signal from the first bank bit cell to a sense amplifier in response to deassertion of the write enable signal for the first bank bit cell and to couple a data bit output signal from the second bank bit cell to the sense amplifier in response to deassertion of the write enable signal for the second bank bit cell. The shared read path and the shared write path are further configured to operate simultaneously such that a read operation to one of the banks may occur while a write operation to the other bank occurs.

Inventors

• H.LI
• A - C - Kota
• D. Xie Si
• B.Liang
• C.ZHENG

Assignees

• 高通股份有限公司

Dates

Publication Date

20260505

Application Date

20240604

Priority Date

20230710

Claims (20)

1. 1. A memory, the memory comprising: A first bank bit cell arranged in rows and columns; a first bank column multiplexer configured to select a column from the first bank bit cells; A second bank bit cell arranged in rows and columns; A second bank column multiplexer configured to select a column from the second bank bit cells, and Input/output circuitry including a common read path coupled to the first and second bank column multiplexers and including a common write path coupled to the first and second bank column multiplexers.
2. 2. The memory of claim 1, the memory further comprising: a controller configured to control timing of a first read operation of the first bank bit cell through the common read path and to control timing of a first write operation of the second bank bit cell through the common write path, wherein the first read operation is concurrent with the first write operation.
3. 3. The memory of claim 2, wherein the controller is further configured to control timing of a second read operation to the second bank bit cell through the common read path and to control timing of a second write operation to the first bank bit cell through the common write path, wherein the second read operation is concurrent with the second write operation.
4. 4. The memory of claim 2, the memory further comprising: A first duplicate column, and And wherein the controller is coupled to the first replicated column and the second replicated column.
5. 5. The memory of claim 2, wherein the common read path comprises: A sense amplifier, and wherein the controller is further configured to assert a sense enable signal to the sense amplifier.
6. 6. The memory of claim 1, wherein the common write path comprises a write driver, and wherein a data input terminal common to the first bank column multiplexer and to the second bank column multiplexer is coupled to the write driver, and wherein a complementary data input terminal common to the first bank column multiplexer and to the second bank multiplexer is also coupled to the write driver.
7. 7. The memory of claim 1, wherein each column in the first bank bit cells comprises a corresponding bit line pair, and wherein the first bank column multiplexer is coupled to a bit line in the corresponding bit line pair for a selected column in the first bank bit cells and to a complementary bit line in the corresponding bit line pair.
8. 8. The memory of claim 6, wherein the common write path further comprises: a level shifter configured to level shift the data input signal in response to a memory supply voltage for the memory to form a level shifted data input signal.
9. 9. The memory of claim 8, wherein the common write path further comprises: A buffer configured to buffer the level shifted data input signal to form a buffered data input signal and a complementary buffered data input signal.
10. 10. The memory of claim 9, wherein the common write path further comprises: a write driver configured to drive the data input terminal with a write driver input signal in response to the buffered data input signal to drive the complementary data input terminal with a complementary write driver input signal in response to the complementary buffered data input signal.
11. 11. The memory of claim 5, wherein the sense amplifier includes an input terminal coupled to a data bit output terminal shared by the first bank column multiplexer and by the second bank column multiplexer, and includes a complementary input terminal coupled to a complementary data bit output terminal shared by the first bank column multiplexer and by the second bank column multiplexer.
12. 12. The memory of claim 11, wherein the shared read path further comprises a data output latch and a level shifter configured to level shift a data output signal from the sense amplifier to form a level shifted data output signal and latch the level shifted data output signal to form a data output signal for the shared read path.
13. 13. The memory of claim 1, wherein each bit cell in the first bank bit cell and in the second bank bit cell is a six transistor bit cell.
14. 14. The memory of claim 1, wherein the memory is integrated into a cellular telephone.
15. 15. A method of operation for a memory, the method comprising: Coupling a first data input signal through a common write path to form a first write driver input signal at a data input terminal, the data input terminal being common to a first bank column multiplexer of a first bank bit cell and to a second bank column multiplexer of a second bank bit cell; In response to assertion of a write enable signal for the first bank bit cell, coupling the first write driver input signal through the first bank column multiplexer to write to the first bank bit cell during a first write operation; Coupling a second data input signal through the common write path to form a second write driver input signal at the data input terminal, and The second write driver input signal is coupled through the second bank column multiplexer to write to the second bank bit cell during a second write operation in response to assertion of a write enable signal for the second bank bit cell.
16. 16. The method of claim 15, the method further comprising: coupling a first data bit output signal from the second bank bit cell through the second bank column multiplexer to a data bit output terminal shared by the first bank column multiplexer and by the second bank column multiplexer during a first read operation in response to deassertion of the write enable signal for the second bank bit cell, and The first data bit output signal from the data bit output terminal is coupled to a sense amplifier in a common read path during the first read operation, wherein the first write operation is concurrent with the first read operation.
17. 17. The method of claim 16, the method further comprising: coupling a second data bit output signal from the first bank bit cell to the data bit output terminal through the first bank column multiplexer during a second read operation in response to deassertion of the write enable signal for the first bank bit cell, and The second data bit output signal from the data bit output terminal is coupled to the sense amplifier during the second read operation, wherein the second write operation is concurrent with the second read operation.
18. 18. The method of claim 15, the method further comprising: During the first write operation, coupling a first complementary data input signal through the common write path to form a first complementary write driver input signal at a first complementary data input terminal shared by the first bank column multiplexer and by the second bank column multiplexer, and The first complementary write driver input signal is coupled to the first bank bit cell through the first bank column multiplexer during the first write operation.
19. 19. The method of claim 16, the method further comprising: Coupling, by the second column multiplexer, a first complementary data bit output signal from the second column unit during the first read operation to a complementary data output terminal shared by the first column multiplexer and by the second column multiplexer, and The first complementary data bit output signal from the complementary data output terminal is coupled to the sense amplifier during the first read operation.
20. 20. A memory, the memory comprising: a first bin unit; A second bank bit unit, and A common write path configured to couple a write driver input signal to the first bank bit cell in response to assertion of a write enable signal for the first bank bit cell and to couple the write driver input signal to the second bank bit cell in response to assertion of a write enable signal for the second bank bit cell.

Description

High-speed and area-efficient parallel read-write memory Technical Field The present application relates to integrated circuit memories, and more particularly to an integrated circuit memory with parallel write and read operations. Background Integrated circuit memory, such as Static Random Access Memory (SRAM), includes bit cells arranged in rows and columns. Each row is traversed by a corresponding word line. As the number of bit cells increases, it is effective to arrange the bit cells into banks such that each bank has its own row and corresponding word line. Each bank will typically have its own input/output (I/O) circuitry including a read path and a write path to the bit cells of the bank. Disclosure of Invention According to one aspect of the disclosure, a memory is provided that includes a first bank bit cell arranged in rows and columns, a first bank column multiplexer configured to select a column from the first bank bit cell, a second bank bit cell arranged in rows and columns, a second bank column multiplexer configured to select a column from the second bank bit cell, and an input/output circuit including a common read path coupled to the first bank column multiplexer and the second bank column multiplexer, and including a common write path coupled to the first bank column multiplexer and the second bank column multiplexer. According to another aspect of the present disclosure, there is provided an operating method for a memory, the method comprising coupling a first data input signal through a common write path to form a first write driver input signal at a first data input terminal, the first data input terminal being shared by a first bank column multiplexer of a first bank bit cell and by a second bank column multiplexer of a second bank bit cell, coupling the first write driver input signal through the first bank column multiplexer to write to the first bank bit cell during a first write operation in response to assertion of a write enable signal for the first bank bit cell, coupling a second data input signal through the common write path to form a second write driver input signal at the first data input terminal, and coupling the second write driver input signal through the second bank column multiplexer to write to the second bank bit cell during a second write operation in response to assertion of a write enable signal for the second bank bit cell. According to yet another aspect of the present disclosure, a memory is provided that includes a first bank bit cell, a second bank bit cell, and a common write path configured to couple a write driver input signal to the first bank bit cell in response to assertion of a write enable signal for the first bank bit cell, and to couple the write driver input signal to the second bank bit cell in response to assertion of a write enable signal for the second bank bit cell. These and other advantageous features will be better understood from the detailed description that follows. Drawings FIG. 1 illustrates an SRAM including a pair of banks accessed through a common I/O circuit including a common read path and a common write path for the banks in accordance with an aspect of the disclosure. FIG. 2 illustrates an I/O portion of an SRAM in accordance with an aspect of the present disclosure. FIG. 3 illustrates an example bitcell for an SRAM in accordance with an aspect of the present disclosure. FIG. 4 is a flow chart of a method for operation of a memory in which two banks share a write path, according to an aspect of the present disclosure. FIG. 5 illustrates some example electronic systems including integrated circuits with memory having a pair of banks and a common I/O circuit according to an aspect of the disclosure. The detailed implementation of the present disclosure and its advantages are best understood by referring to the detailed description that follows. It should be understood that like reference numerals are used to identify like elements illustrated in one or more of the figures. Detailed Description SRAM may be designed such that all of its bitcells form a single bank/array arranged in rows and columns. A corresponding word line passes through each row and a corresponding bit line pair passes through each column. But as the number of bit cells in the array increases, the row and column lengths correspondingly increase. The resulting word lines and bit lines may then have excessive capacitance, resulting in reduced memory speed. Thus, the bit cells are typically arranged into banks. Each bank has its own rows and columns. Word lines for one bank are not shared by another bank. In this way, the SRAM may include a relatively large number of bit cells without the word lines and bit lines becoming excessively long. Although partitioning the bitcells into banks is highly advantageous with respect to reducing word line and bit line lengths, each bank then typically has its own supporting circuitry, such as input/output (I/O) circuitry for