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CN-121986439-A - Voltage mode control for a multi-level power converter

CN121986439ACN 121986439 ACN121986439 ACN 121986439ACN-121986439-A

Abstract

Circuits and methods for controlling the generation of PWM clock signals for M-level converter cells so that no regulation is lost when transitioning across dead zones and large output current and voltage spikes are avoided or significantly reduced. Embodiments utilize a voltage mode control system in which the 3-state PWM duty cycle is linearly related to the compensation voltage V COMP that can be sensed and directly manipulated. When switching between regions is sensed from V COMP , embodiments alternate the duty cycles of pairs of adjacent PWM periods to achieve a smooth transition. Within the dead zone, a first period of a pair of adjacent PWM periods has a 2-state duty cycle with an upper voltage that increases in duration during the transition sequence and a second period of the pair of adjacent PWM periods has a 2-state duty cycle with a lower voltage that decreases in duration during the transition sequence.

Inventors

  • Daniel. week
  • Gregory Shzesinsky

Assignees

  • 派赛公司

Dates

Publication Date
20260505
Application Date
20240809
Priority Date
20230831

Claims (20)

  1. 1. A Pulse Width Modulation (PWM) generator for a multi-level converter unit is configured to transition from a first operating region to a second operating region through an operating dead zone and to generate a PWM period having a 3-state duty cycle in the operating dead zone, a first state of the 3-state duty cycle comprising a discharge voltage state D, a second state of the 3-state duty cycle comprising a neutral voltage state N, and a third state of the 3-state duty cycle comprising a charge voltage state C, wherein a voltage level of the neutral voltage state N is between a voltage level of the discharge voltage state D and a voltage level of the charge voltage state C.
  2. 2. The PWM generator according to claim 1, wherein the 3-state duty cycle of the PWM period may be implemented as one of a sequence DCN, DNC, CDN, CND, NCD or NDC.
  3. 3. The PWM generator according to claim 1, wherein the PWM generator starts and ends the 3-state duty cycle in response to an external signal.
  4. 4. The PWM generator according to claim 1, wherein the PWM generator uses an open loop feed forward method to start and end the 3-state duty cycle.
  5. 5. The PWM generator according to claim 1, wherein the PWM generator uses a closed loop method to start and end the 3-state duty cycle.
  6. 6. The PWM generator according to claim 1, wherein the PWM generator starts or ends the 3-state duty cycle based on the selected parameter being within or outside a predefined range.
  7. 7. The PWM generator according to claim 1, wherein the PWM generator sets the duration of one of the charge voltage state C or the discharge voltage state D by using an open loop feed forward method.
  8. 8. The PWM generator according to claim 1, wherein the PWM generator sets the duration of one of the charge voltage state C or the discharge voltage state D by using a closed loop method.
  9. 9. The PWM generator according to claim 1, wherein the PWM generator sets the duration of one of the charging voltage state C or the discharging voltage state D based on the selected parameter being within or outside a predefined range.
  10. 10. The PWM generator according to claim 1, wherein the PWM generator sets the duration D 1 of the charging voltage state C and the duration D 2 of the discharging voltage state D such that the sum of D 1 +D 2 is equal to the selected constant.
  11. 11. A method of transitioning from a first operating region of a Pulse Width Modulation (PWM) generator to a second operating region of the PWM generator through an operational dead zone includes generating a PWM period having a 3-state duty cycle in the operational dead zone, a first state of the 3-state duty cycle including a discharge voltage state D, a second state of the 3-state duty cycle including a neutral voltage state N, and a third state of the 3-state duty cycle including a charge voltage state C, wherein a voltage level of the neutral voltage state N is between a voltage level of the discharge voltage state D and a voltage level of the charge voltage state C.
  12. 12. The method of claim 11, wherein the 3-state duty cycle of the PWM period may be implemented as one of a sequence DCN, DNC, CDN, CND, NCD or NDC.
  13. 13. The method of claim 11, wherein the PWM generator starts and ends the 3-state duty cycle in response to an external signal.
  14. 14. The method of claim 11, further comprising starting and ending the 3-state duty cycle using an open loop feed forward method.
  15. 15. The method of claim 11, further comprising starting and ending the 3-state duty cycle using a closed loop method.
  16. 16. The method of claim 11, further comprising starting or ending the 3-state duty cycle based on the selected parameter being within or outside a predefined range.
  17. 17. The method of claim 11, further comprising setting a duration of one of the charge voltage state C or the discharge voltage state D using an open loop feed forward method.
  18. 18. The method of claim 11, further comprising setting a duration of one of the charge voltage state C or the discharge voltage state D using a closed loop method.
  19. 19. The method of claim 11, further comprising setting a duration of one of the charge voltage state C or the discharge voltage state D based on the selected parameter being within or outside of a predefined range.
  20. 20. The method of claim 11, further comprising setting a duration D 1 of the charge voltage state C and a duration D 2 of the discharge voltage state D such that the sum of D 1 +D 2 is equal to the selected constant.

Description

Voltage mode control for a multi-level power converter Cross Reference to Related Applications The present application claims priority from U.S. patent application Ser. No. 63/619,088, filed on 1/9 at 2024, and U.S. patent application Ser. No. 63/579,889, filed on 31 at 2023, the contents of both U.S. patent applications being incorporated herein by reference in their entirety. Background (1) Technical field The present invention relates to electronic circuits, and more particularly to a multi-level power converter (multi-level power converter). (2) Background art Many electronic devices, particularly mobile computing and/or communication products and components (e.g., notebook computers, ultrabook computers, and tablet devices), may be powered from multiple sources, including batteries, solar cells, and rectified AC sources (e.g., USB chargers or wireless charging circuitry). Direct current power converters are typically used to generate lower or higher voltages from a selected power source (e.g., a rectified AC power source) to both power an electronic device and to charge a battery internal to the electronic device. A power converter that generates a lower output voltage level from a higher input voltage power supply is often referred to as a buck converter, so called because the output voltage V OUT is less than the input voltage V IN, and thus the converter "steps down" the input voltage. A power converter that generates a higher output voltage level from a lower input voltage power supply is often referred to as a boost converter because V OUT is greater than V IN. Some power converters may be buck converters or boost converters, depending on which terminals are used for input and output. Some power converters may provide an inverted output. Fig. 1 is a block diagram of a prior art power converter 100. In the illustrated example, the power converter 100 includes a multi-level (M-level) converter unit 102 and a controller 104. The M-level shifter unit 102 is configured to receive an input voltage V IN from a voltage source 106 (e.g., a rectified AC source) across terminals v1+, V1- (common), and to transform the input voltage V IN into an output voltage V OUT across terminals v2+, V2- (common). The output voltage V OUT is typically coupled across the output capacitor C OUT, and a load 108 (e.g., a battery and/or electronics) may be connected across the output capacitor C OUT. The controller 104 receives a set of input signals and generates a set of output signals. Some of these input signals arrive along a signal path 110 connected to the converter unit 102. Some of the input signals carry information indicative of the operational state of the converter unit 102. The controller 104 also typically receives a clock/timing signal CLK and one or more external input/output signals I/O, which may be analog, digital (encoded or direct signal lines), or a combination of both. Based on the received input signals, the controller 104 provides a set of control signals (including a clock signal phi 1,……φn) back to the converter unit 102 on the signal path 110, which set of control signals control internal components (e.g., internal power switches, such as FETs, in particular MOSFETs) of the converter unit 102 to cause the converter unit 102 to convert V IN to V OUT. Each power switch will typically have a level shifter and driver circuit coupled to a control input (e.g., the gate of a FET implementing the power switch) to enable the power switch to be turned on or off based on a logic level clock and/or a control signal. In some embodiments, auxiliary circuitry (not shown) may provide various signals such as clock signal CLK, input/output signal I/O, and various voltages such as general system supply voltage V DD and at least one transistor bias voltage V BIAS to controller 104 (and optionally directly to converter unit 102). One type of M-level converter cell 102 includes a charge transfer capacitor as an energy storage element coupled through a controlled power switch to transfer charge from V IN to V OUT. Such charge transfer capacitors are commonly referred to as "flying capacitors" or "pump capacitors. Each time a flying capacitor is used (i.e., not bypassed), the electrical energy flowing through the flying capacitor will typically charge or discharge the flying capacitor. For example, fig. 2 is a schematic diagram of a prior art 3-level converter cell 200. The conductive channels (drain-to-source) of power Field Effect Transistors (FETs) M0-M3 are coupled in series between an input voltage V IN and a reference potential (e.g., circuit ground). Clock signals phi 0 to phi 3 from the Pulse Width Modulation (PWM) generator circuit 202 applied (directly or indirectly) to the respective power FETs M0 to M3 control the on (turned on) or off (turned off) states of the power FETs (note that level shifting, drivers and control circuitry are omitted for simplicity). The PWM generator circuit 202 generates clock signals