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CN-121986444-A - LDPC decoder with reduced complexity

CN121986444ACN 121986444 ACN121986444 ACN 121986444ACN-121986444-A

Abstract

The present disclosure relates to a method and receiver device configured to implement a reduced complexity Low Density Parity Check (LDPC) decoder. The method may include performing a first set of decoding iterations on an encoded codeword received in a transmission from a transmitter. The method may further include performing a second set of decoding iterations on the encoded codeword if the first set of decoding iterations did not successfully decode the encoded codeword, wherein the second set of decoding iterations performs a check node update on a partial set of check nodes of the matrix. If the second set of decoding iterations yields a decoded codeword, then a network operation based on the decoded codeword may be performed.

Inventors

  • Matias Anderson
  • LIU QINGCHAO

Assignees

  • 瑞典爱立信有限公司

Dates

Publication Date
20260505
Application Date
20231011

Claims (20)

  1. 1. A method for implementing a reduced complexity low density parity check, LDPC, decoder in a receiver device (800), the method comprising: -receiving (302) a transmission comprising an encoded codeword from a transmitter device (1002); Performing (304) a first set of decoding iterations on the encoded codeword, the first set of decoding iterations performing check node updates on all check nodes of a matrix; Performing (306) a second set of decoding iterations on the encoded codeword in response to the first set of decoding iterations not resulting in a decoded codeword, the second set of decoding iterations performing a check node update on a partial set of check nodes of the matrix, wherein the second set of decoding iterations is performed after the first set of decoding iterations, and A network operation based on the decoded codeword is performed (314) in response to the second set of decoding iterations resulting in a decoded codeword.
  2. 2. The method of claim 1, further comprising: performing (308) hard decisions on bits of the encoded codeword after the second set of decoding iterations, and Determining (310) that bits of the encoded codeword satisfy a corresponding parity check equation, resulting in the decoded codeword.
  3. 3. The method of any of claims 1-2, wherein the first set of decoding iterations is at most a first predetermined number of iterations and the second set of decoding iterations is at most a second predetermined number of iterations.
  4. 4. A method according to claim 3, wherein the first predetermined number of iterations is ten.
  5. 5. The method of any of claims 3 to 4, wherein the second predetermined number of iterations is at most ten.
  6. 6. The method of any of claims 1-2, wherein the first set of decoding iterations results in a message from at least one variable node having a degree greater than one to a check node, the log likelihood ratio of the message being less than a threshold based on a minimum log likelihood ratio for all variable nodes having a degree of2 or higher.
  7. 7. The method of any one of claims 1 to 6, further comprising: a third set of decoding iterations is performed (313), wherein the second set of decoding iterations and the third set of decoding iterations are performed for different sets of check nodes.
  8. 8. The method of claim 7, wherein the different sets of check nodes are based on a modulation and coding scheme used for the encoded codeword.
  9. 9. The method of claim 8, wherein the different set of check nodes is based on an expected reliability of variable nodes having a degree of 1 or higher.
  10. 10. The method of any of claims 1 to 9, wherein a check node update is performed for a second set of decoding iterations of the encoded codeword for a set of check nodes in the matrix that are not associated with variable nodes of degree 1.
  11. 11. The method of any one of claims 1 to 10, further comprising: Responsive to determining that bits of the encoded codeword satisfy a respective parity check equation, the performing (312) of the second set of decoding iterations is stopped.
  12. 12. A receiver device (800) configured to implement a reduced complexity low density parity check, LDPC, decoder, the receiver device (800) comprising a radio interface and processing circuitry configured to: -receiving (302) a transmission comprising an encoded codeword from a transmitter device (1002); Performing (304) a first set of decoding iterations on the encoded codeword, the first set of decoding iterations performing check node updates on all check nodes of a matrix; Performing (306) a second set of decoding iterations on the encoded codeword in response to the first set of decoding iterations not resulting in a decoded codeword, the second set of decoding iterations performing a check node update on a partial set of check nodes of the matrix, wherein the second set of decoding iterations is performed after the first set of decoding iterations, and A network operation based on the decoded codeword is performed (314) in response to the second set of decoding iterations resulting in a decoded codeword.
  13. 13. The receiver device (800) of claim 12, wherein the processing circuit is further configured to: performing (308) hard decisions on bits of the encoded codeword after the second set of decoding iterations, and Determining (310) that bits of the encoded codeword satisfy a corresponding parity check equation, resulting in the decoded codeword.
  14. 14. The receiver device (800) of any of claims 12-13, wherein the first set of decoding iterations is at most a first predetermined number of iterations and the second set of decoding iterations is at most a second predetermined number of iterations.
  15. 15. The receiver device (800) of claim 14, wherein the first predetermined number of iterations is ten.
  16. 16. The receiver device (800) of any of claims 14-15, wherein the second predetermined number of iterations is at most ten.
  17. 17. The receiver device (800) of any of claims 12-13, wherein the first set of decoding iterations results in a message from at least one variable node with a degree greater than 1 to a check node, and the log likelihood ratio of the message is less than a threshold based on a minimum log likelihood ratio for all variable nodes with degrees of 2 or higher.
  18. 18. The receiver device (800) of any of claims 12-17, wherein the processing circuit is further configured to: a third set of decoding iterations is performed (313), wherein the second set of decoding iterations and the third set of decoding iterations are performed for different sets of check nodes.
  19. 19. The receiver device (800) of claim 18, wherein the different set of check nodes is based on a modulation and coding scheme used for the encoded codeword.
  20. 20. The receiver device (800) of claim 19, wherein the different set of check nodes is based on an expected reliability of variable nodes having a degree of 1 or higher.

Description

LDPC decoder with reduced complexity Technical Field The present disclosure relates to a reduced complexity Low Density Parity Check (LDPC) decoder in a wireless communication system. Background The New Radio (NR) Low Density Parity Check (LDPC) code is a code rate compatible LDPC code. Code rate compatibility is achieved by a large number of variable nodes with degree 1. LDPC codes are readily described by a Parity Check Matrix (PCM) 102 as shown in fig. 1, where rows and columns correspond to check nodes and variable nodes, respectively. As shown in fig. 1, each of the PCMs 102 corresponds to an edge 104 between a check node 106 and a variable node 108. The parity check matrix may be mapped to a bipartite graph consisting of check nodes and variable nodes, wherein rows and columns of PCM correspond to the check nodes and variable nodes, respectively. Each entry H (i, j) =1 in PCM corresponds to an edge between a check node and a variable node. In various embodiments disclosed herein, parity check matrices, or bipartite graphs may be referred to interchangeably. For example, check nodes of the matrix or variable nodes of the matrix may be referenced, whereby binary check nodes or variable nodes of the bipartite graph to which the parity check matrix can be mapped are being referenced. The NR LDPC code belongs to code rate compatible LDPC code series based on prototype graph. They also have quasi-circularity. The quasi-cyclic parity check matrix is divided into square sub-blocks (sub-matrices) of size Z x Z. These sub-matrices are cyclic permutations of the identity matrix or null sub-matrices. The cyclic permutation matrix Pi is obtained by cyclic shifting the columns of the z×z identity matrix by i elements to the right. The matrix P0 is a z×z identity matrix. The quasi-cyclic LDPC code is conveniently described by a base matrix (base matrix), which is a matrix in which each integer i represents a cyclic permutation matrix Pi. An entry in the matrix with i= -1 represents a zero (0) submatrix. The basic structure of the PCM 102 is shown in fig. 2. The figure shows the case where the first 2 xz systematic bits are always punctured (i.e., punctured bits 204), a structure that has been proven to reduce the code threshold. Some of the remaining systematic bits are always transmitted, while if the desired block length Ktx, ktx < K, where K is the original block length of the Parity Check Matrix (PCM), some of the remaining systematic bits can be shortened. The first Mb Z parity bits and the bits corresponding to one to three degree 1 columns provide the highest code rate codeword. The code rate may be reduced by transmitting additional parity bits from the incremental redundancy portion (as described by the rightmost portion of the matrix). Some parity bits may be punctured in the case of shortening or in the case where the desired code rate is higher than the highest design code rate. There are two sets of LDPC codewords defined for NR. One of which is designed for a code rate of from about 8/9 to 1/3 and a block length of up to 8448 bits (base pattern #1, also referred to as BG # 1), and the other of which is defined for a code rate of from about 2/3 to 1/5 and a block length of up to 3840 bits (base pattern #2 or BG # 2). When these LDPC codes are used at a lower code rate than the design value, repetition and chase (chase) combining is used to achieve a lower code rate. The LDPC code is iteratively decoded by a message passing algorithm. In hierarchical scheduling, a set of check nodes is processed at a time. The equivalent representation we will use is to process check nodes one by one. The decoder uses memory for each variable node. This is done by observing the log-likelihood ratio (LLR) through the channelInitialized (from soft demapping) and used to represent the confidence of the decoder in the value of the bit and the strength of this confidence. Each connection between check node i and variable node j (referred to as) There is also a memory for holding previous messages from check node i to variable node j. These are initialized to 0. In the check node update step, a message from the check node to each of its neighboring variable nodes is calculated. The message is then used to update the confidence of the variable node。 In d.e. "A reduced complexity decoder architecture via layered decoding of LDPC codes"（IEEE Workshop on Signal Processing Systems,2004,SIPS 2004, pages 107 to 112 of hocevar), first, the check node obtains confidence about its value from the connected variable node, where the old message from the check node is subtracted: Based on nodes from all other connected variables To calculate new messages from the check node to each connected variable node: using the message to update the confidence level for variable node j: Finally, update : The values that need to be held in memory between check nodes areAnd. After each check node is calculated, it may be discardedAnd。 There are several p