CN-121986462-A - Hash circuit based on hybrid ring generator

Abstract

A hash circuit includes an n-bit hybrid ring generator configured to implement an n-degree primitive polynomial, a phase shifter coupled to an output of the n-bit hybrid ring generator, and an m-bit nonlinear sequential device coupled to an output of the phase shifter. The n-bit hybrid ring generator includes n state elements coupled to each other to form an n-bit ring structure, k feedback enable devices, and an injection device configured to inject bits of a binary value into the n-bit ring structure. The n-bit ring structure has a top row and a bottom row, each of the top row and the bottom row having at least one of n state elements and at least one of k feedback-enabling devices. The m-bit nonlinear sequential device includes m state elements coupled to each other to form an m-bit ring structure, and one or more feedback paths including nonlinear devices implementing nonlinear functions.

Inventors

• Janaz Rajski
• M. Zhuoka
• Jackie tyzer
• B. Verdzak

Assignees

• 西门子工业软件有限公司

Dates

Publication Date

20260505

Application Date

20230809

Claims (20)

1. 1. A hash circuit configured to convert a binary value to a hash value, comprising: An n-bit hybrid ring generator configured to implement an n-degree primitive polynomial, the n-bit hybrid ring generator comprising n state elements coupled to each other to form an n-bit ring structure in a schematic, k feedback enable devices, and an injection device configured to inject bits of a binary value into the n-bit ring structure, the n-bit ring structure having a top row and a bottom row, each of the top row and the bottom row having at least one of the n state elements and at least one of the k feedback enable devices, each of the k feedback enable devices coupled to a state element on a different row through one of k feedback lines; A phase shifter coupled to the output of the n-bit hybrid ring generator, and An m-bit nonlinear sequential device coupled to the output of the phase shifter, the m-bit nonlinear sequential device comprising m state elements coupled to each other to form an m-bit ring structure in a schematic, and one or more feedback paths comprising nonlinear devices, each nonlinear device configured to implement a nonlinear function that converts bits of the output from some of the m state elements to one bit.
2. 2. The hash circuit of claim 1, further comprising: a plurality of 2-to-1 multiplexers interposed between the phase shifter and the m-bit nonlinear sequential device, a select input of the plurality of 2-to-1 multiplexers coupled to an output of a state element of the m state elements.
3. 3. The hash circuit of claim 1, wherein the number of state elements placed on the top row and the bottom row of the n state elements is equal to or differs by one, the number of feedback-enabling devices placed on the top row and the bottom row of the k feedback-enabling devices is equal to or differs by one, k is greater than 2, none of the k feedback lines cross each other, and the feedback lines coupled to the feedback-enabling devices on the top row and the feedback lines coupled to the feedback-enabling devices on the bottom row alternate with respect to each other.
4. 4. The hash circuit of claim 3, wherein the k feedback lines are distributed such that the number of two sets of state elements on the top row or the bottom row is equal or differs by no more than two between any three adjacent feedback lines or between two adjacent feedback lines and the end points of their adjacent ring structures.
5. 5. The hash circuit of claim 1, wherein the n-bit hybrid ring generator further comprises: Feedback path selection memory device, and The feedback path selects the logic device and, Wherein the feedback path selection storage device and the feedback path selection logic device are configured to enable the n-bit hybrid ring generator to implement one of a plurality of n-th order primitive polynomials based on feedback configuration bits stored in the storage device.
6. 6. The hash circuit of claim 1, wherein the n-bit hybrid ring generator is configured to receive an initial value before the circuit begins converting the binary value to the hash value.
7. 7. The hash circuit of claim 1, wherein the nonlinear function is a derivative of bent functions, and the derivative of bent functions is a balanced boolean function.
8. 8. The hash circuit of claim 1, wherein each of the nonlinear devices comprises: bent function means configured to implement a bent function, the bent function receiving bits at outputs from the plurality of state elements; An AND gate having an input coupled to the output of the bent function device and to one of the outputs of the plurality of state elements, and Circuitry configured to combine the output of the bent function device with the output of the and gate into one bit and inject that bit into the m-bit ring structure.
9. 9. The hash circuit of claim 1, wherein the nonlinear function-based device is configured to receive an initial value before the circuit begins converting the binary value to the hash value.
10. 10. The hash circuit of claim 1, wherein the n state elements and the m state elements are flip-flops, the k feedback enable devices and the injection device are exclusive-or gates, and the phase shifter comprises an exclusive-or gate.
11. 11. One or more computer-readable media storing computer-executable instructions for causing a computer to perform a method comprising: creating a hash circuit in a circuit design, the hash circuit comprising: An n-bit hybrid ring generator configured to implement an n-degree primitive polynomial, the n-bit hybrid ring generator comprising n state elements coupled to each other to form an n-bit ring structure in a schematic, k feedback enable devices, and an injection device configured to inject bits of a binary value into the n-bit ring structure, the n-bit ring structure having a top row and a bottom row, each of the top row and the bottom row having at least one of the n state elements and at least one of the k feedback enable devices, each of the k feedback enable devices coupled to a state element on a different row through one of k feedback lines; A phase shifter coupled to the output of the n-bit hybrid ring generator, and An m-bit nonlinear sequential device coupled to the output of the phase shifter, the m-bit nonlinear sequential device comprising m state elements coupled to each other to form an m-bit ring structure in a schematic, and one or more feedback paths comprising nonlinear devices, each nonlinear device configured to implement a nonlinear function that converts bits of the output from some of the m state elements to one bit.
12. 12. The one or more computer-readable media of claim 11, wherein the hash circuit further comprises: a plurality of 2-to-1 multiplexers interposed between the phase shifter and the m-bit nonlinear sequential device, a select input of the plurality of 2-to-1 multiplexers coupled to an output of a state element of the m state elements.
13. 13. The one or more computer-readable media of claim 11, wherein the number of state elements of the n state elements placed on the top row and the bottom row is equal to or differs by one, the number of feedback-enabling devices of the k feedback-enabling devices placed on the top row and the bottom row is equal to or differs by one, k is greater than 2, none of the k feedback lines cross each other, and the feedback lines of the feedback-enabling devices coupled to the top row and the feedback lines of the feedback-enabling devices coupled to the bottom row are alternately placed with respect to each other.
14. 14. The one or more computer-readable media of claim 13, wherein the k feedback lines are distributed such that the number of two sets of state elements on the top row or the bottom row is equal or differs by no more than two between any three adjacent feedback lines, or between two adjacent feedback lines and the endpoints of their adjacent ring structures.
15. 15. The one or more computer-readable media of claim 11, wherein the n-bit hybrid ring generator further comprises: Feedback path selection memory device, and The feedback path selects the logic device and, Wherein the feedback path selection storage device and the feedback path selection logic device are configured to enable the n-bit hybrid ring generator to implement one of a plurality of n-th order primitive polynomials based on feedback configuration bits stored in the storage device.
16. 16. The one or more computer-readable media of claim 11, wherein the n-bit hybrid ring generator is configured to receive an initial value before the circuitry begins converting the binary value to the hash value.
17. 17. The one or more computer-readable media of claim 11, wherein the nonlinear function is a derivative of bent functions and the derivative of bent functions is a balanced boolean function.
18. 18. The one or more computer-readable media of claim 11, wherein each of the nonlinear devices comprises: bent function means configured to implement a bent function, the bent function receiving bits at outputs from the plurality of state elements; An AND gate having an input coupled to the output of the bent function device and to one of the outputs of the plurality of state elements, and Circuitry configured to combine the output of the bent function device with the output of the and gate into one bit and inject that bit into the m-bit ring structure.
19. 19. The one or more computer-readable media of claim 11, wherein a nonlinear function-based device is configured to receive an initial value before the circuit begins converting the binary value to the hash value.
20. 20. The one or more computer-readable media of claim 11, wherein the n state elements and the m state elements are flip-flops, the k feedback enable devices and the injection device are exclusive-or gates, and the phase shifter comprises an exclusive-or gate.

Description

Hash circuit based on hybrid ring generator Technical Field The disclosed technology relates to the field of hardware security and trust. Various implementations of the disclosed technology may be particularly suitable for hash circuit design and applications. Background Hash functions play a variety of roles in protecting the digital ecosystem. Cryptographic hashing is critical to many network-related security and information security applications, including data integrity, entity authentication, digital signature, encryption key generation, cryptographic security, forensic investigation, transaction integrity in blockchains, and message authentication in the internet of things. For example, if a password is entered in a website, the server may store a hashed version of the password. Similarly, hashing protects website connections and cryptocurrency transactions. On the other hand, the non-cryptographic hash function may make file processing more efficient in a large data center. Cryptographic hash functions play a critical role in shaping the basis on which the secure operation of a digital Integrated Circuit (IC) depends for a high-end hardware trust root. Typically, they are integrated into the circuit as custom security modules, handling chip and device identities, managing encryption keys and functions, and protecting security boots, authentication, identity verification, and firmware updates. Thus, the hardware trust root should be able to detect intrusions, disable access and/or confuse the logic operation of the IC while waiting for further operation. The basis of a silicon-based fixed function trust root is its authentication protocol. It performs a specific set of functions such as true random number generation, data encryption, key verification, logical locking, and data hashing. As an initial part of the actual challenge-response procedure, the IC creates a truly random token, often referred to as a challenge or random number (which may also contain some individual data from the IC, such as its electronic identification number), which is then sent to the secure server. The secure processor calculates a hash value of the random number. The hash value (or digest) is then returned to the IC for comparison with a locally (internally) generated hash value by the IC. The latter is typically done by a device implementing a lightweight cryptographic hash function. Lightweight cryptographic hash circuits have become a critical hardware security primitive. It should be able to generate an almost unique and fixed length digest for an arbitrarily long input sequence, even in small devices with limited computational resources. However, many IC vendors may still not consider conventional solutions acceptable due to their not so lightweight hardware and complex implementation. Therefore, it would be highly desirable to have a hash circuit that is lightweight, compact, programmable, scalable, and capable of easy conversion to a key hash scheme. Disclosure of Invention Various aspects of the disclosed technology relate to hash circuits built based on hybrid ring generators. In one aspect, a hash circuit is provided that is configured to convert binary values to hash values, comprising an n-bit hybrid torus generator configured to implement n-degree primitive polynomials, the n-bit hybrid torus generator comprising n state elements coupled to each other through one feedback line of k feedback lines to form an n-bit torus structure in a schematic, k feedback enable devices, and an injection device configured to inject bits of binary values into the n-bit torus structure, the n-bit torus structure having top and bottom rows, each of the top and bottom rows having at least one state element of the n state elements and at least one feedback enable device of the k feedback enable devices, each of the k feedback enable devices coupled to a state element on a different row through one feedback line of k feedback lines, a phase shifter coupled to an output of the n-bit hybrid torus generator, and an m-bit nonlinear device configured to sequentially inject bits of binary values into the n-bit torus structure, each of the top and bottom rows having at least one state element of the n state elements and at least one feedback enable device of the k feedback enable devices, the k feedback enable devices coupled to each of the m state elements in a linear nonlinear path comprising the m state nonlinear element and the m nonlinear device configured to form a nonlinear function of the m state nonlinear path. The circuit may further include a plurality of 2-to-1 multiplexers interposed between the phase shifter and the m-bit nonlinear sequential devices, the select inputs of the plurality of 2-to-1 multiplexers being coupled to the outputs of the state elements of the m state elements. The number of state elements placed on the top row and the bottom row of the n state elements may be equal or differ by one, the number of feedba