CN-121986466-A - Low power automatically scalable differential pre-driver

Abstract

The transmitter includes a driver slice coupled to an output of the transmitter. Each driver slice includes a first differential pre-driver that is selectively enabled and disabled by a first switch based on a control code configuration. The second differential pre-driver provides the first differential buffered data signal to the first set of driver slices when the second differential pre-driver is enabled. The second switch enables the second differential predriver when the control code is configured to enable the first differential predriver in at least one driver slice of the first set of driver slices. When the third differential pre-driver is enabled, the third differential pre-driver provides a second differential buffered data signal to the second set of driver slices. The third switch enables the third differential predriver when the control code is configured to enable the first differential predriver in at least one driver slice of the second set of driver slices.

Inventors

• N. Saputra
• S. Wardward

Assignees

• 高通股份有限公司

Dates

Publication Date

20260505

Application Date

20240918

Priority Date

20231012

Claims (20)

1. 1. A transmitter circuit coupled to a data communication link, the transmitter circuit comprising: A driver slice coupled to an output of the transmitter circuit, each driver slice comprising: A first differential pre-driver, and A first switch configured to selectively enable and disable the first differential pre-driver of the each driver slice based on a configuration of control code provided to the transmitter circuit; A second differential pre-driver configured to provide a first differential buffered data signal to the inputs of the first set of driver slices when the second differential pre-driver is enabled; A second switch configured to enable the second differential predriver when one or more bits of the control code are configured to enable the first differential predriver in at least one driver slice of the first set of driver slices; a third differential pre-driver configured to provide a second differential buffered data signal to an input of each of a second set of driver slices when the third differential pre-driver is enabled, and A third switch configured to enable the third differential predriver when one or more bits of the control code are configured to enable the first differential predriver in at least one driver slice of the second set of driver slices.
2. 2. The transmitter circuit of claim 1, wherein each driver slice of the first set of driver slices is excluded from the second set of driver slices.
3. 3. The transmitter circuit of claim 1, wherein the first set of driver slices comprises more driver slices than the second set of driver slices.
4. 4. The transmitter circuit of claim 1, the transmitter circuit further comprising: a fourth differential pre-driver configured to propagate a differential input data signal to the second differential pre-driver when the fourth differential pre-driver is enabled, and A fourth switch configured to enable a first differential pre-driver in at least one driver slice of the first set of driver slices when the fourth differential pre-driver is enabled.
5. 5. The transmitter circuit of claim 4, wherein the fourth differential pre-driver is further configured to propagate the differential input data signal to the third differential pre-driver when a first differential pre-driver in at least one driver slice of the second set of driver slices is enabled.
6. 6. The transmitter circuit of claim 4, the transmitter circuit further comprising: A fifth differential pre-driver configured to propagate the differential input data signal to the third differential pre-driver when the fifth differential pre-driver is enabled, and A fifth switch configured to enable a first differential pre-driver in at least one driver slice of the second set of driver slices when the fifth differential pre-driver is enabled.
7. 7. The transmitter circuit of claim 6, wherein the fourth differential pre-driver is configured to propagate the differential input data signal to a first set of buffer circuits including the second differential pre-driver, and the fifth differential pre-driver is configured to propagate the differential input data signal to a second set of buffer circuits including the third differential pre-driver, wherein the second set of buffer circuits includes more buffer circuits than the first set of buffer circuits, and wherein at least one buffer in the transmitter circuit is disabled when the first set of buffer circuits or the second set of buffer circuits are enabled.
8. 8. The transmitter circuit of claim 1, wherein each driver slice further comprises: A differential voltage driver having an output coupled to the output of the transmitter circuit and an input coupled to the output of the first differential pre-driver in each driver slice.
9. 9. The transmitter circuit of claim 1, the transmitter circuit further comprising: a pull-down transistor coupled to an output of at least one driver slice, wherein the pull-down transistor is turned on when the first differential pre-driver of the at least one driver slice is disabled.
10. 10. The transmitter circuit of claim 1, the transmitter circuit further comprising: A pull-up transistor coupled to an output of at least one driver slice, wherein the pull-up transistor is turned on when the first differential pre-driver of the at least one driver slice is disabled.
11. 11. An apparatus, the apparatus comprising: means for enabling a first differential pre-driver in a driver slice when indicated by a control code, the means comprising: a first switch configured to enable the first differential pre-driver of a first driver slice disposed in a first set of driver slices, and A second first switch configured to enable the first differential pre-driver of a second driver slice disposed in a second set of driver slices, and Means for enabling a buffer circuit when indicated by the control code, the means comprising: A second differential pre-driver enabled when the first driver slice is enabled, wherein the second differential pre-driver is configured to provide a first differential buffered data signal to the inputs of the first group of driver slices when the second differential pre-driver is enabled, and A third differential pre-driver enabled when the second driver slice is enabled, wherein the third differential pre-driver is configured to provide a second differential buffered data signal to the inputs of the second group of driver slices when the third differential pre-driver is enabled.
12. 12. The apparatus of claim 11, wherein each driver slice of the first set of driver slices is excluded from the second set of driver slices.
13. 13. The device of claim 11, wherein the first set of driver slices comprises more driver slices than the second set of driver slices.
14. 14. The apparatus of claim 11, wherein a fourth differential pre-driver is configured to propagate a differential input data signal to the second differential pre-driver when the fourth differential pre-driver is enabled, and wherein the fourth differential pre-driver is enabled when a first differential pre-driver in at least one driver slice in the first set of driver slices is enabled.
15. 15. The apparatus of claim 14, wherein the fourth differential pre-driver is further configured to propagate the differential input data signal to the third differential pre-driver when a first differential pre-driver in at least one driver slice in the second set of driver slices is enabled.
16. 16. The apparatus of claim 14, wherein a fifth differential pre-driver is configured to propagate the differential input data signal to the third differential pre-driver when the fifth differential pre-driver is enabled, wherein the fifth differential pre-driver is enabled when a first differential pre-driver in at least one driver slice in the second set of driver slices is enabled.
17. 17. The apparatus of claim 16, wherein the fourth differential pre-driver is configured to propagate the differential input data signal to a first set of buffer circuits including the second differential pre-driver, and the fifth differential pre-driver is configured to propagate the differential input data signal to a second set of buffer circuits including the third differential pre-driver, wherein the second set of buffer circuits includes more buffer circuits than the first set of buffer circuits, and wherein at least one buffer in the apparatus is disabled when the first set of buffer circuits or the second set of buffer circuits are enabled.
18. 18. The apparatus of claim 11, the apparatus further comprising: means for driving an output of the device, the means comprising differential voltage drivers in the driver slices, wherein each differential voltage driver has an output coupled to the output of the device and an input coupled to an output of the first differential pre-driver in the driver slices of the differential voltage drivers.
19. 19. The apparatus of claim 11, the apparatus further comprising: a pull-down transistor coupled to an output of at least one driver slice, wherein the pull-down transistor is turned on when the first differential pre-driver of the at least one driver slice is disabled.
20. 20. The apparatus of claim 11, the apparatus further comprising: A pull-up transistor coupled to an output of at least one driver slice, wherein the pull-up transistor is turned on when the first differential pre-driver of the at least one driver slice is disabled.

Description

Low power automatically scalable differential pre-driver Cross Reference to Related Applications This patent application claims priority from pending U.S. non-provisional application No. 18/485,882, filed on 10 months 12 of 2023, which is assigned to the assignee of the present application and is hereby expressly incorporated by reference as if fully set forth below and for all applicable purposes. Technical Field The present disclosure relates generally to high speed interfaces and, more particularly, to pre-driver circuitry disposed in a transmitter in a high speed interface. Background Electronic device technology has seen explosive growth over the past few years. For example, better communications, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer a range of ever expanding features and services to their customers and offer users unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular telephones, tablet computers, laptop computers, etc.) have become more powerful and complex than ever before. A wireless device may include a high-speed bus interface for signal communication between hardware components. High-speed serial buses offer advantages over parallel communication links when reduced power consumption and smaller footprints are required, for example, in Integrated Circuit (IC) devices. In a serial interface, a serializer is used to convert data from parallel words to a serial bit stream, and a deserializer is used to convert data back to parallel words at the receiver. For example, the high speed bus interface may be implemented using a peripheral component interconnect express (PCIe) bus, universal Serial Bus (USB), or Serial Advanced Technology Attachment (SATA), or the like. Physical layer (PHY) circuits for providing high-speed bus interfaces in IC devices typically use parallel layers of driver circuits to provide sufficient drive capability and/or match bus impedance. The layers of the driver circuit are driven by a pre-driver circuit that consumes a significant portion of the power used by the PHY circuit and sometimes consumes an excess portion. There is a continuing need for new and efficient PHY circuits that consume less power. Disclosure of Invention Certain aspects of the present disclosure relate to systems, devices, methods, and techniques that may be used to reduce power consumption in a transmitter disposed in a high-speed bus interface circuit. In one aspect, the low power automatically scalable differential pre-driver may be configured to enable or disable the pre-driver circuit based on the number or combination of layers of the driver circuit configured to drive lines of the high speed bus. In various aspects of the disclosure, a transmitter circuit coupled to a data communication link includes driver slices coupled to an output of the transmitter circuit, each driver slice having a first differential pre-driver and a first switch configured to selectively enable and disable the first differential pre-driver of each driver slice based on a configuration of a control code provided to the transmitter circuit. The transmitter circuit has a second differential pre-driver configured to provide the first differential buffered data signal to the input of the first set of driver slices when the second differential pre-driver is enabled and a second switch configured to enable the second differential pre-driver when the one or more bits of the control code are configured to enable the first differential pre-driver in at least one of the first set of driver slices. The transmitter circuit has a third differential pre-driver configured to provide a second differential buffered data signal to an input of each of the second set of driver slices when the third differential pre-driver is enabled, and a third switch configured to enable the third differential pre-driver when one or more bits of the control code are configured to enable the first differential pre-driver in at least one of the second set of driver slices. In various aspects of the disclosure, an apparatus includes means for enabling a first differential pre-driver in a driver slice when indicated by a control code and means for enabling a buffer circuit when indicated by the control code. The means for enabling the first differential pre-driver in the driver slices may include a first switch configured to enable the first differential pre-driver of the first driver slices disposed in the first group of driver slices and a second first switch configured to enable the first differential pre-driver of the second driver slices disposed in the first group of driver slices. The means for enabling the buffer circuit when indicated by the control code may include a second differential pre-driver en