CN-121986563-A - Memory cell, memory array, memory and electronic equipment

Abstract

The embodiment of the application provides a memory unit, a memory array, a memory and electronic equipment, relates to the technical field of semiconductor memory, and is used for relieving the problem of high power consumption of a ferroelectric memory. The storage capacitor of the storage unit comprises a first electrode, a ferroelectric layer, a first metal oxide layer and a second electrode. The first metal oxide layer is arranged between the first electrode and the ferroelectric layer in a layer-by-layer manner. The metal element of the first metal oxide in the first metal oxide layer comprises at least one metal element except hafnium element in the third group, the fourth group and the fifth group, and the first metal oxide layer applies proper pulling force to the ferroelectric layer to stretch the crystal structure of the ferroelectric layer, so that the crystal structure of the ferroelectric layer has lattice distortion to increase the proportion of O phase in the ferroelectric layer, thereby increasing the ferroelectricity of the ferroelectric layer, enabling the memory to realize ferroelectric polarity inversion more easily, and reducing the working voltage and power consumption.

Inventors

• YU FANGZHOU
• HUAN YAHUAN
• FENG ZEXIN
• LIANG ZHONGXIN
• WU JIALU
• ZHANG HENG
• XU JUNHAO

Assignees

• 华为技术有限公司

Dates

Publication Date

20260505

Application Date

20231020

Claims (20)

1. The memory cell is characterized by comprising a transistor and a storage capacitor electrically connected with the transistor, wherein the storage capacitor comprises: a first electrode; a ferroelectric layer laminated with the first electrode, the ferroelectric layer being a doped hafnium oxide based ferroelectric layer; A first metal oxide layer stacked between the first electrode and the ferroelectric layer, wherein the first metal oxide layer includes a first metal oxide, and a metal element in the first metal oxide includes at least one metal element other than hafnium in a third group, a fourth group or a fifth group; and the second electrode is arranged on one side of the ferroelectric layer, which is away from the first electrode, in a stacking way.
2. The memory cell of claim 1, wherein, The dielectric constant of the first metal oxide layer is larger than that of the ferroelectric layer, and the dielectric constant of the first metal oxide layer is smaller than that of the first electrode.
3. The memory cell of claim 1 or 2, wherein the storage capacitor further comprises: And a second metal oxide layer stacked between the second electrode and the ferroelectric layer, wherein the second metal oxide layer includes a second metal oxide, and a metal element in the second metal oxide includes at least one metal element other than hafnium in a third group, a fourth group or a fifth group.
4. The memory cell of claim 3 wherein, The dielectric constant of the second metal oxide layer is larger than that of the ferroelectric layer, and the dielectric constant of the second metal oxide layer is smaller than that of the second electrode.
5. The memory cell of any of claims 1-4, wherein the storage capacitor comprises a plurality of the first metal oxide layers, each of which is: A first bottom metal oxide layer; And the first top metal oxide layer is arranged on one side of the first bottom metal oxide layer, which is away from the first electrode, in a lamination manner, wherein the materials of the first top metal oxide layer and the first bottom metal oxide layer are different.
6. The memory cell of any of claims 1-5, wherein the storage capacitor further comprises: The first transition layer is arranged between the first electrode and the first metal oxide layer in a stacked mode, and comprises a third metal oxide, wherein metal elements in the third metal oxide are the same as at least one metal element of the first electrode.
7. The memory cell of any of claims 3-6, wherein the storage capacitor further comprises: the second transition layer is arranged between the second electrode and the second metal oxide layer in a stacked mode, and comprises a fourth metal oxide, wherein metal elements in the fourth metal oxide are the same as at least one metal element of the second electrode.
8. The memory cell of claim 6 or 7, wherein, The first electrode comprises tungsten and the third metal oxide comprises tungsten oxide; Or alternatively The first electrode comprises titanium and the third metal oxide comprises titanium oxide; Or alternatively The first electrode comprises ruthenium and the third metal oxide comprises ruthenium oxide.
9. The memory cell of claim 1, wherein the first metal oxide comprises at least one of yttria, scandia, lanthana, ceria, titania, niobia, tantala, or vanadia.
10. The memory cell of claim 2, wherein the first metal oxide comprises at least one of lanthanum oxide, cerium oxide, titanium oxide, niobium oxide, tantalum oxide, or vanadium oxide.
11. The memory cell of any of claims 1-10, wherein the first metal oxide layer has a thickness of 0.5nm to 2nm.
12. The memory cell of any of claims 1-11, wherein the ferroelectric layer has a thickness of 3nm to 20nm.
13. The memory cell of any of claims 1-12, wherein the ferroelectric layer comprises hafnium oxide and a doping material comprising at least one of zirconium, titanium, niobium, lanthanum, cerium, gadolinium, yttrium, aluminum, or strontium.
14. The memory cell is characterized by comprising a transistor and a storage capacitor electrically connected with the transistor, wherein the storage capacitor comprises: A first metal oxide layer; A ferroelectric layer stacked on the first metal oxide layer; the ferroelectric layer is a doped hafnium oxide-based ferroelectric layer, the first metal oxide layer comprises a first metal oxide, and metal elements in the first metal oxide comprise at least one metal element except hafnium element in elements of a third group, a fourth group or a fifth group, wherein the dielectric constant of the first metal oxide layer is larger than that of the ferroelectric layer; The ferroelectric device comprises a ferroelectric layer, a first metal oxide layer, a second metal oxide layer and a second metal oxide layer, wherein the first metal oxide layer is arranged on one side of the ferroelectric layer far away from the first metal oxide layer in a lamination mode, the dielectric constant of the first metal oxide layer is larger than that of the ferroelectric layer, the second metal oxide layer comprises a second metal oxide, and metal elements in the second metal oxide comprise at least one metal element except hafnium in a third group, a fourth group or a fifth group.
15. The memory cell of claim 14, wherein the storage capacitor comprises a plurality of the first metal oxide layers of: A first bottom metal oxide layer; And the first top metal oxide layer is arranged on one side of the first bottom metal oxide layer facing the ferroelectric layer in a lamination manner, wherein the materials of the first top metal oxide layer and the first bottom metal oxide layer are different.
16. The memory cell of claim 14 or 15, wherein the first metal oxide comprises at least one of lanthanum oxide, cerium oxide, titanium oxide, niobium oxide, tantalum oxide, or vanadium oxide.
17. A memory array, comprising: a first electrode line; A second electrode line; A third electrode line; A memory cell according to any one of claims 1 to 13, or a memory cell according to any one of claims 14 to 16; the control end of the transistor is electrically connected with the first electrode wire, the first electrode of the transistor is electrically connected with the second electrode wire, and the second electrode of the transistor is electrically connected with the third electrode wire through the storage capacitor.
18. A memory array, comprising: the storage capacitor comprises a second electrode wire, a third electrode wire and a storage capacitor, wherein the storage capacitor comprises: a first electrode electrically connected to the second electrode line; a ferroelectric layer laminated with the first electrode, the ferroelectric layer being a doped hafnium oxide based ferroelectric layer; A first metal oxide layer stacked between the first electrode and the ferroelectric layer, wherein the first metal oxide layer includes a first metal oxide, and a metal element in the first metal oxide includes at least one metal element other than hafnium in a third group, a fourth group or a fifth group; And the second electrode is arranged on one side of the ferroelectric layer, which is away from the first electrode, in a stacking way, and is electrically connected with the third electrode wire.
19. The memory array of claim 18, wherein the memory array is configured to store, The dielectric constant of the first metal oxide layer is larger than that of the ferroelectric layer, and the dielectric constant of the first metal oxide layer is smaller than that of the first electrode.
20. A memory, comprising: a memory array as claimed in claim 17, 18 or 19; And the controller is electrically connected with the storage array and is used for controlling the reading and writing of the storage array.

Description

Memory cell, memory array, memory and electronic equipment Technical Field The present application relates to the field of semiconductor memory technologies, and in particular, to a memory unit, a memory array, a memory, and an electronic device. Background Non-volatile memory is increasingly required in electronic devices because it is capable of storing data even when power is removed, as compared to volatile memory. Ferroelectric memories include, as a nonvolatile memory, a ferroelectric material having an electric dipole whose different polarities can be switched by adjusting a voltage applied to the ferroelectric material to switch between different polarization states, thereby realizing the storage of binary numbers "1" and "0". However, the ferroelectric memory has the problem of high power consumption at present, which affects the application range of the ferroelectric memory. Disclosure of Invention The application provides a memory cell, a memory array, a memory and electronic equipment, which are used for relieving the problem of high power consumption of a ferroelectric memory. In order to achieve the above purpose, the application adopts the following technical scheme: In one aspect of the present application, a memory cell is provided that includes a transistor and a storage capacitor electrically connected to the transistor. The storage capacitor may include a first electrode, a ferroelectric layer, a first metal oxide layer, and a second electrode. Wherein the ferroelectric layer is laminated with the first electrode, and the ferroelectric layer is a doped hafnium oxide-based ferroelectric layer. The first metal oxide layer is arranged between the first electrode and the ferroelectric layer in a layer-by-layer manner. The first metal oxide layer may be configured to stretch the crystal structure of the ferroelectric layer such that the crystal structure of the ferroelectric layer has lattice distortion. Wherein the first metal oxide layer includes a first metal oxide, and the metal element in the first metal oxide may include at least one metal element other than hafnium in the group III, group IV or group V elements. Furthermore, the second electrode layer stack is arranged on the side of the ferroelectric layer facing away from the first electrode. In summary, the first electrode, the ferroelectric layer, the first metal oxide layer and the second electrode may form a storage capacitor. When there is a voltage difference between the first electrode and the second electrode, the polarization direction (up-polarization or down-polarization) of the ferroelectric material in the ferroelectric layer may be changed to realize a read operation of the storage capacitor for storing data. Further, since the first metal oxide may include at least one metal element other than hafnium among group iii, group iv, or group v elements, the lattice structure after crystallization of the first metal oxide layer is similar to that after crystallization of the ferroelectric layer, so that chemical bonds are easily formed near the interface of the first metal oxide layer and the ferroelectric layer. And, in the course that the first metal oxide layer and the ferroelectric layer are converted from amorphous structure to crystalline structure, the first metal oxide layer can stretch the crystalline structure of the ferroelectric layer, so that a proper stress is generated near the interface of the first metal oxide layer and the ferroelectric layer. The stress may cause the lattice of the ferroelectric layer and the lattice of the first metal oxide layer to be mismatched to form a dislocation such that the lattice structure of the ferroelectric layer has lattice distortion. The lattice distortion makes the asymmetry of the lattice structure of the ferroelectric layer larger, increases the proportion of O phase in the ferroelectric layer, and can increase the ferroelectricity of the ferroelectric layer because O phase is the main reason for ferroelectricity generated by the doped hafnium oxide-based electric material. The ferroelectric property of the ferroelectric layer is enhanced, so that the ferroelectric layer can be easily inverted in polarity, and the coercive electric field E C of the memory cell can be reduced. Since the coercive electric field E C is proportional to the operation electric field and the operation voltage, the operation electric field and the operation voltage of the memory cell can be reduced, and the power consumption of the memory cell and the memory with the memory cell can be reduced. In an alternative embodiment, the dielectric constant of the first metal oxide layer is greater than the dielectric constant of the ferroelectric layer, and the dielectric constant of the first metal oxide layer is less than the dielectric constant of the first electrode. In this way, the first metal oxide layer has a strong capacity of storing charges, and when the working voltage is applied to two side