CN-121986565-A - Semiconductor structure and manufacturing method thereof

Abstract

The disclosed semiconductor device includes first and second semiconductor stacks vertically stacked. The first semiconductor stack includes a first memory array layer including a first memory cell array, a first peripheral circuit layer including a first transistor formed on the first semiconductor layer, and a first interconnect structure extending vertically through the first semiconductor stack, between adjacent first memory cell arrays, and extending through the first semiconductor layer. The second semiconductor stack includes a second memory array layer including second memory cell arrays, a second peripheral circuit layer including second transistors formed on the second semiconductor layer, and a second interconnect structure extending vertically through the second semiconductor stack, between adjacent second memory cell arrays, and through the second semiconductor layer. The first interconnect structure is in contact with the second interconnect structure, and the first semiconductor layer faces the second semiconductor layer.

Inventors

• XIAO LIANG
• WEN MIN
• ZHAO DAI
• ZHOU WENBIN
• HUO ZONGLIANG

Assignees

• 长江存储控股股份有限公司

Dates

Publication Date

20260505

Application Date

20240830

Claims (20)

1. 1. A semiconductor structure, comprising: A first semiconductor stack comprising: a first memory array layer including a first array of memory cells, A first peripheral circuit layer on the first memory array layer and including a first transistor formed on a first semiconductor layer, an A first interconnect structure extending vertically through the first semiconductor stack, between adjacent first memory cell arrays, and through the first semiconductor layer, and A second semiconductor stack comprising: A second memory array layer including a second array of memory cells, A second peripheral circuit layer on the second memory array layer and including a second transistor formed on a second semiconductor layer, an A second interconnect structure extending vertically through the second semiconductor stack, between adjacent second memory cell arrays, and through the second semiconductor layer, Wherein the first semiconductor stack is bonded with the second semiconductor stack such that the first interconnect structure is in contact with the second interconnect structure and the first semiconductor layer faces the second semiconductor layer.
2. 2. The semiconductor structure of claim 1, wherein each of the first and second arrays of memory cells comprises: a transistor layer comprising an array of vertical transistors, each vertical transistor comprising a vertically extending channel structure, and A storage layer vertically stacked on the transistor layer and including an array of capacitors, each capacitor coupled with a corresponding one of the vertical transistor arrays.
3. 3. The semiconductor structure of claim 1, wherein: the first semiconductor stack and the second semiconductor stack are hybrid bonded to each other, and The first conductive plate of the first interconnect structure is in contact with the second conductive plate of the second interconnect structure.
4. 4. The semiconductor structure of claim 3, wherein the first conductive plate and the second conductive plate are embedded in a bonding layer comprising carbon nitride.
5. 5. The semiconductor structure of claim 3, wherein the first conductive plate and the second conductive plate are embedded in a bonding layer comprising silicon oxide.
6. 6. The semiconductor structure of claim 1, wherein a thickness of the first semiconductor stack or the second semiconductor stack is less than 12 μιη.
7. 7. The semiconductor structure of claim 1, wherein the first memory array layer is bonded to the first peripheral circuit layer, and The second memory array layer is bonded to the second peripheral circuit layer.
8. 8. The semiconductor structure of claim 1, wherein the first semiconductor stack further comprises a first bridge contact structure extending laterally between the first semiconductor layer and the second semiconductor layer and extending vertically through the first semiconductor layer twice to interconnect two of the first transistors, and The second semiconductor stack further includes a second bridge contact structure extending laterally between the first semiconductor layer and the second semiconductor layer and extending vertically through the second semiconductor layer twice to interconnect two of the second transistors.
9. 9. The semiconductor structure of claim 2, wherein the capacitor array comprises: a plurality of first electrodes coupled to the vertical transistor array, and A plurality of second electrodes coupled to the common conductive layer.
10. 10. The semiconductor structure of claim 9, wherein the common conductive layer comprises: a main transverse plate in contact with the plurality of second electrodes; a vertical plate contacting the edge of the main transverse plate, and A lateral landing portion in contact with the vertical plate and in contact with a capacitor interconnect structure coupled with the first transistor or the second transistor.
11. 11. A semiconductor structure, comprising: A first semiconductor stack comprising: A first memory array layer comprising: a first memory cell array, and A first through array interconnect structure located between the first memory cell arrays; A first peripheral circuit layer bonded to the first memory array layer, the first peripheral circuit layer comprising: A first transistor formed on the first semiconductor layer, and A first through-circuit interconnect structure extending through the first semiconductor layer and in contact with the first through-array interconnect structure, and A second semiconductor stack comprising: A second memory array layer, comprising: A second memory cell array, and A second through array interconnect structure located between the second memory cell arrays; A second peripheral circuit layer bonded to the second memory array layer, the second peripheral circuit layer comprising: A second transistor formed on the second semiconductor layer, and A second through-circuit interconnect structure extending through the second semiconductor layer and in contact with the second through-array interconnect structure, Wherein the first semiconductor stack is bonded to the second semiconductor stack such that the first through-circuit interconnect structure is in contact with the second through-circuit interconnect structure.
12. 12. The semiconductor structure of claim 11, wherein each of the first and second arrays of memory cells comprises: a transistor layer comprising an array of vertical transistors, each vertical transistor comprising a vertically extending channel structure, and A storage layer vertically stacked on the transistor layer and including an array of capacitors, each capacitor coupled with a corresponding one of the vertical transistor arrays.
13. 13. The semiconductor structure of claim 11, wherein: the first semiconductor stack and the second semiconductor stack are hybrid bonded to each other, and The first conductive plate of the first through circuit interconnect structure is in contact with the second conductive plate of the second through circuit interconnect structure.
14. 14. The semiconductor structure of claim 13, wherein the first conductive plate and the second conductive plate are embedded in a bonding layer comprising carbon nitride.
15. 15. The semiconductor structure of claim 13, wherein the first conductive plate and the second conductive plate are embedded in a bonding layer comprising silicon oxide.
16. 16. The semiconductor structure of claim 11, wherein a thickness of the first semiconductor stack or the second semiconductor stack is less than 12 μιη.
17. 17. The semiconductor structure of claim 11, wherein the first semiconductor layer and the second semiconductor layer are located between the first memory array layer and the second memory array layer.
18. 18. The semiconductor structure of claim 11, wherein: The first semiconductor stack further includes a first bridge contact structure extending laterally between the first semiconductor layer and the second semiconductor layer and extending vertically through the first semiconductor layer twice to interconnect two of the first transistors, and The second semiconductor stack further includes a second bridge contact structure extending laterally between the first semiconductor layer and the second semiconductor layer and extending vertically through the second semiconductor layer twice to interconnect two of the second transistors.
19. 19. The semiconductor structure of claim 12, wherein the capacitor array comprises: a plurality of first electrodes coupled to the vertical transistor array, and A plurality of second electrodes coupled to the common conductive layer.
20. 20. The semiconductor structure of claim 19, wherein the common conductive layer comprises: a main transverse plate in contact with the plurality of second electrodes; a vertical plate contacting the edge of the main transverse plate, and A lateral landing portion in contact with the vertical plate and in contact with a capacitor interconnect structure coupled with the first transistor or the second transistor.

Description

Semiconductor structure and manufacturing method thereof Technical Field The present disclosure relates generally to the field of semiconductor technology, and more particularly, to a semiconductor device and a method of manufacturing the same. Background Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cells approaches the lower limit, planar processing and fabrication techniques become challenging and costly. As a result, the memory density of the planar memory cells approaches the upper limit. A three-dimensional (3D) memory architecture may address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuitry for facilitating operation of the memory array. Disclosure of Invention Some aspects of the present disclosure provide a semiconductor structure including a first semiconductor stack including a first memory array layer including a first memory cell array, a first peripheral circuit layer located on the first memory array layer and including a first transistor formed on the first semiconductor layer, and a first interconnect structure extending vertically through the first semiconductor stack between adjacent first memory cell arrays and extending through the first semiconductor layer, and a second semiconductor stack including a second memory array layer including a second memory cell array, a second peripheral circuit layer located on the second memory array layer and including a second transistor formed on the second semiconductor layer, and a second interconnect structure extending vertically through the second semiconductor stack between adjacent second memory cell arrays and extending through the second semiconductor layer, wherein the second interconnect structure and the second semiconductor stack face the second semiconductor stack with the second semiconductor stack facing the first semiconductor stack. In some embodiments, each of the first memory cell array and the second memory cell array includes a transistor layer including a vertical transistor array, each vertical transistor including a vertically extending channel structure, and a storage layer vertically stacked on the transistor layer and including an array of capacitors, each capacitor coupled to a corresponding one of the vertical transistor arrays. In some embodiments, the first semiconductor stack and the second semiconductor stack are hybrid bonded to each other, and the first conductive plate of the first interconnect structure is in contact with the second conductive plate of the second interconnect structure. In some embodiments, the first conductive plate and the second conductive plate are embedded in a bonding layer comprising carbon nitride. In some embodiments, the first conductive plate and the second conductive plate are embedded in a bonding layer comprising silicon oxide. In some embodiments, the thickness of the first semiconductor stack or the second semiconductor stack is less than 12 μm. In some embodiments, a first memory array layer is bonded to a first peripheral circuit layer and a second memory array layer is bonded to a second peripheral circuit layer. In some embodiments, the first semiconductor stack further includes a first bridge contact structure extending laterally between the first semiconductor layer and the second semiconductor layer and extending vertically through the first semiconductor layer twice to interconnect two of the first transistors, and the second semiconductor stack further includes a second bridge contact structure extending laterally between the first semiconductor layer and the second semiconductor layer and extending vertically through the second semiconductor layer twice to interconnect two of the second transistors. In some embodiments, the capacitor array includes a plurality of first electrodes coupled with the vertical transistor array and a plurality of second electrodes coupled with the common conductive layer. In some embodiments, the common conductive layer includes a main lateral plate in contact with the plurality of second electrodes, a vertical plate in contact with an edge of the main lateral plate, and a lateral landing portion in contact with the vertical plate and in contact with a capacitor interconnect structure coupled with the first transistor or the second transistor. Some other aspects of the present disclosure provide a semiconductor structure including a first semiconductor stack including a first memory array layer including a first memory cell array and a first through array interconnect structure between the first memory cell array, a first peripheral circuit layer bonded to the first memory array layer including a first transistor formed on the first semiconductor layer and a first through circuit interconnect structure extending through the f