CN-121986566-A - Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device includes a silicon carbide layer (12) of a first conductivity type, a plurality of well regions (50) of a second conductivity type provided on the silicon carbide layer (12), a source region (40) of the first conductivity type provided on the well regions (50), a JFET region (20) of the first conductivity type formed on a region of the silicon carbide layer (12) sandwiched by the plurality of well regions (50), an insulating film covering the JFET region (20), and a gate electrode (80) provided on the JFET region (20) via the insulating film. Wherein impurities of the first conductivity type implanted into the JFET region (20) are also implanted into the well region (50). Within the well region (50), the concentration of the second conductivity type impurity is greater than the concentration of the first conductivity type impurity.

Inventors

• Koh tetsuhei
• INOUE HIROTO
• Nakashigaya

Assignees

• 新电元工业株式会社

Dates

Publication Date

20260505

Application Date

20241030

Priority Date

20231117

Claims (7)

1. 1. A silicon carbide semiconductor device, comprising: A silicon carbide layer of a first conductivity type; A plurality of well regions of a second conductivity type disposed on the silicon carbide layer; A source region of a first conductivity type disposed on the well region; JFET regions of a first conductivity type formed in the silicon carbide layer over regions sandwiched by the plurality of well regions; An insulating film covering the JFET region, and A gate electrode provided on the JFET region via the insulating film, Wherein the impurity of the first conductivity type which is implanted into the JFET region is also implanted into the well region, In the well region, a concentration of the second conductivity type impurity is greater than a concentration of the first conductivity type impurity.
2. 2. The silicon carbide semiconductor device according to claim 1, wherein: Wherein the first conductivity type impurity is implanted in a range from the JFET region up to a position below at least a JFET region side end portion of the source region in the well region.
3. 3. The silicon carbide semiconductor device according to claim 1 or 2, wherein: Wherein nitrogen is implanted as the first conductivity type impurity in an upper region and phosphorus is implanted as the first conductivity type impurity in a lower region below the upper region in the well region.
4. 4. A silicon carbide semiconductor device according to claim 3, wherein: wherein the concentration of the nitrogen and the phosphorus is less than the concentration of the second conductivity type impurity at any depth position of the well region.
5. 5. A silicon carbide semiconductor device according to claim 3, wherein: wherein the distance in the depth direction between the lower limit point at which the impurity concentration of nitrogen starts to decrease in the direction in which the depth becomes deeper and the upper limit point at which the impurity concentration of phosphorus starts to decrease in the direction in which the depth becomes shallower is 0.5 [ mu ] m or less.
6. 6. A silicon carbide semiconductor device according to claim 3, wherein: Wherein the difference between the highest value of the impurity concentration of nitrogen and the highest value of the impurity concentration of phosphorus is within 20%.
7. 7. A method for manufacturing a silicon carbide semiconductor device, comprising: Forming a plurality of well regions of a second conductivity type in the silicon carbide layer of the first conductivity type; Forming a source region of a first conductivity type in the well region; Forming a JFET region in a region of the silicon carbide layer sandwiched by the plurality of well regions by implanting first conductivity type impurities into a region of the silicon carbide layer sandwiched by the plurality of well regions and a region of the well region on the silicon carbide layer side; A step of forming an insulating film covering the JFET region, and A step of forming a gate electrode provided on the JFET region via the insulating film, Wherein, in the well region, the concentration of the second conductive type impurity is greater than the concentration of the first conductive type impurity.

Description

Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device Technical Field The present invention relates to a silicon carbide semiconductor device having a JFET region and a method for manufacturing the silicon carbide semiconductor device. Background Conventionally, a silicon carbide semiconductor device including a JFET region is known, and for example, patent No. 7127748 discloses a silicon carbide semiconductor device including a semiconductor substrate made of silicon carbide, a drift layer made of a silicon carbide semiconductor of a first conductivity type formed on the semiconductor substrate, one or more well regions of a second conductivity type formed on a surface layer portion of the drift layer, a JFET region of the first conductivity type which is a part of the drift layer sandwiched by the well regions, and a source region of the first conductivity type formed on a surface side in the well region so as to be separated from the drift layer, wherein an impurity concentration of the first conductivity type is higher than an impurity concentration of the drift layer. In a practical silicon carbide semiconductor device, when the JFET concentration is high, sufficient withstand voltage cannot be ensured when the JFET region is completely connected to the well region, and therefore, the JFET region and the well region are generally separated to form a region having a low impurity concentration. On the other hand, if such a region having a low impurity concentration is present, there is a problem that on-resistance increases. In view of the above, an object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device, which can suppress on-resistance and ensure sufficient withstand voltage. Disclosure of Invention [ Concept 1] The silicon carbide semiconductor device of the present invention includes: A silicon carbide layer of a first conductivity type; A plurality of well regions of a second conductivity type disposed on the silicon carbide layer; A source region of a first conductivity type disposed on the well region; JFET regions of a first conductivity type formed in the silicon carbide layer over regions sandwiched by the plurality of well regions; An insulating film covering the JFET region, and A gate electrode provided on the JFET region via the insulating film, Wherein the impurity of the first conductivity type which is implanted into the JFET region is also implanted into the well region, In the well region, a concentration of the second conductivity type impurity is greater than a concentration of the first conductivity type impurity. [ Concept 2] In the silicon carbide semiconductor device based on concept 1, The first conductivity type impurity may be implanted in a range from the JFET region up to a position below at least a JFET region side end portion of the source region in the well region. [ Concept 3] In the silicon carbide semiconductor device based on concept 1 or 2, Nitrogen may be implanted as the first conductivity type impurity in the well region in an upper region, and phosphorus may be implanted as the first conductivity type impurity in a lower region below the upper region. [ Concept 4] In the silicon carbide semiconductor device based on concept 3, At any depth of the well region, the concentrations of the nitrogen and the phosphorus are less than the concentration of the second conductivity type impurity. [ Concept 5] In the silicon carbide semiconductor device based on concept 3 or 4, The distance in the depth direction between the lower limit point at which the impurity concentration of nitrogen starts to decrease in the direction in which the depth becomes deeper and the upper limit point at which the impurity concentration of phosphorus starts to decrease in the direction in which the depth becomes shallower is 0.5 [ mu ] m or less. [ Concept 6] In the silicon carbide semiconductor device based on concept 3, The difference between the highest value of the impurity concentration of nitrogen and the highest value of the impurity concentration of phosphorus is within 20%. [ Concept 7] The method for manufacturing a silicon carbide semiconductor device of the present invention comprises: Forming a plurality of well regions of a second conductivity type in the silicon carbide layer of the first conductivity type; Forming a source region of a first conductivity type in the well region; Forming a JFET region in a region of the silicon carbide layer sandwiched by the plurality of well regions by implanting first conductivity type impurities into a region of the silicon carbide layer sandwiched by the plurality of well regions and a region of the well region on the silicon carbide layer side; A step of forming an insulating film covering the JFET region, and A step of forming a gate electrode provided on the JFET region via the insulating fi