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CN-121986567-A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

CN121986567ACN 121986567 ACN121986567 ACN 121986567ACN-121986567-A

Abstract

The semiconductor device includes a chip having a main surface, a drift region of a first conductivity type formed on a surface layer portion of the main surface, a trench electrode type gate structure formed on the main surface so as to be located in the drift region, and a well region of a second conductivity type formed along a bottom wall of the gate structure in a region below the gate structure in the drift region, wherein the well region includes a plurality of first well regions having a first bottom portion having a first depth, the plurality of first well regions being formed at a first interval in a depth direction of the gate structure, and adjacent first well regions being opposed to each other in the depth direction of the gate structure with a portion of the drift region interposed therebetween.

Inventors

  • HE LIYI
  • Sen Chengwu

Assignees

  • 罗姆股份有限公司

Dates

Publication Date
20260505
Application Date
20240919
Priority Date
20231016

Claims (16)

  1. 1. A semiconductor device, comprising: A chip having a main surface; A drift region of the first conductivity type formed in a surface layer portion of the main surface; A trench electrode type gate structure formed on the main surface so as to be located in the drift region, A well region of a second conductivity type formed along a bottom wall of the gate structure in a region below the gate structure within the drift region, The well region includes a plurality of first well regions having a first bottom portion having a first depth, the plurality of first well regions being formed at first intervals in a depth direction of the gate structure, Adjacent first well regions are opposed to each other in the depth direction of the gate structure with a portion of the drift region interposed therebetween.
  2. 2. The semiconductor device according to claim 1, wherein, The chip includes SiC.
  3. 3. The semiconductor device according to claim 1 or 2, wherein, The first spacing is greater than the first depth of the first well region.
  4. 4. A semiconductor device according to any one of claim 1 to 3, wherein, The well region further includes a second well region formed between the plurality of first well regions in a manner connected to the plurality of first well regions and having a second bottom portion having a second depth shallower than the first depth.
  5. 5. The semiconductor device according to claim 4, wherein, The ratio of the second depth to the first depth is less than 0.5.
  6. 6. The semiconductor device according to claim 4 or 5, wherein, And a body region penetrating the gate structure, the body region being formed on the main surface side with respect to the drift region in a surface layer portion of the main surface, The first depth is greater than a thickness of the body region, The second depth is less than a thickness of the body region.
  7. 7. The semiconductor device according to claim 6, wherein, The body region extends along a sidewall of the gate structure in the depth direction of the gate structure, The body region is connected to the well region.
  8. 8. The semiconductor device according to any one of claims 4 to 7, wherein, Further comprising a second conductivity type high concentration well region formed in the well region from the first bottom of the first well region toward the bottom wall side of the gate structure at a spacing and having a higher impurity concentration than the well region, The second bottom of the second well region is located at the drift region, The high concentration well region has a bottom portion located closer to a bottom wall side of the gate structure than the second bottom portion of the second well region.
  9. 9. The semiconductor device according to any one of claims 4 to 8, wherein, Further comprising a second conductivity type high concentration well region formed in the well region from the first bottom portion of the first well region toward the bottom wall side of the gate structure at a spacing and having an impurity concentration higher than that of the well region, The second bottom of the second well region is located at the same height as the bottom of the high concentration well region.
  10. 10. The semiconductor device according to any one of claims 1 to 9, wherein, And a channel region of a second conductivity type formed along a sidewall of the gate structure, A clamped portion of the drift region, which is clamped by the adjacent first well region, is formed in a channel lower region of the gate structure below a portion forming the channel region.
  11. 11. The semiconductor device according to claim 10, wherein, The first well region is not formed in the under-channel region.
  12. 12. The semiconductor device according to claim 10, wherein, The first well region includes a region formed in the under-channel region.
  13. 13. The semiconductor device according to claim 12, wherein, The first well region has a first region that meets the clamped portion from one side in the depth direction of the gate structure in the channel lower region.
  14. 14. The semiconductor device according to claim 13, wherein, The first well region further has a second region that meets the clamped portion from the other side of the depth direction of the gate structure in the channel lower region.
  15. 15. The semiconductor device according to any one of claims 10 to 14, wherein, The first well region is formed in the gate structure in a non-channel lower region below a region where the channel region is not formed, The clamped portion is not formed in the non-channel lower region.
  16. 16. The semiconductor device according to claim 15, wherein, In the non-channel lower region, the first well region is formed in an entire region of the gate structure in the depth direction.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips RELATED APPLICATIONS The present application corresponds to Japanese patent application No. 2023-178289, filed by the Japanese patent office at 10/16 of 2023, the entire disclosure of which is incorporated herein by reference. Technical Field The present disclosure relates to a semiconductor device. Background Patent document 1 discloses a semiconductor device including a semiconductor substrate, a semiconductor region, a body region, a gate trench, a gate insulating film, a gate electrode, and a p-type diffusion region. The semiconductor region is formed on the upper surface side of the semiconductor substrate. The body region is formed on the upper surface side of the semiconductor substrate than the semiconductor region. A gate trench is formed on an upper surface of the semiconductor substrate and penetrates the body region. The gate insulating film covers the wall surface of the gate trench. The gate electrode is buried in the gate trench via a gate insulating film. A p-type diffusion region is formed in the semiconductor region along a bottom wall of the gate trench. Prior art literature Patent literature Patent document 1 U.S. patent application publication No. 2010/0224932 specification Disclosure of Invention An embodiment of the present disclosure provides a semiconductor device capable of realizing a reduction in resistance while suppressing a reduction in withstand voltage. One embodiment of the present disclosure provides a semiconductor device including a chip having a main surface, a drift region of a first conductivity type formed in a surface layer portion of the main surface, a trench electrode type gate structure formed in the main surface so as to be located in the drift region, and a well region of a second conductivity type formed along a bottom wall of the gate structure in a region below the gate structure in the drift region. The well region includes a plurality of first well regions having a first bottom portion having a first depth, the plurality of first well regions being formed at first intervals in a depth direction of the gate structure. The adjacent first well regions are opposed to each other in the depth direction of the gate structure with a part of the drift region interposed therebetween. Drawings Fig. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. Fig. 2 is a sectional view taken along line II-II shown in fig. 1. Fig. 3 is a plan view showing an example of the layout of a chip. Fig. 4 is an enlarged view of a portion surrounded by the one-dot chain line IV of fig. 3. Fig. 5 is a sectional view taken along the line V-V shown in fig. 4. Fig. 6 is a sectional view taken along the VI-VI line shown in fig. 4. Fig. 7 is a cross-sectional view taken along line VII-VII shown in fig. 4. Fig. 8 is an enlarged view of a portion surrounded by the one-dot chain line VIII of fig. 5. Fig. 9 is an enlarged view of a portion surrounded by the one-dot chain line IX of fig. 6. Fig. 10 is a cross-sectional view of the semiconductor device according to the reference embodiment, and corresponds to fig. 6. Fig. 11 is a cross-sectional view of the semiconductor device according to the reference embodiment, and corresponds to fig. 7. Fig. 12 is a plan view showing an example of the layout of a chip according to the second embodiment of the present disclosure, and corresponds to fig. 4. Fig. 13 is a cross-sectional view taken along line XIII-XIII shown in fig. 12. Fig. 14 is a cross-sectional view taken along line XIV-XIV shown in fig. 12. Fig. 15 is a cross-sectional view taken along the line XV-XV shown in fig. 12. Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in fig. 12. Fig. 17 is an enlarged view of a portion surrounded by the one-dot chain line XVII of fig. 15. Fig. 18 is a cross-sectional view of the semiconductor device according to the first modification, and corresponds to fig. 16. Fig. 19 is a cross-sectional view of the semiconductor device according to the second modification, and corresponds to fig. 9. Fig. 20 is a cross-sectional view of a semiconductor device according to a third modification, and corresponds to fig. 5. Fig. 21 is a cross-sectional view of a semiconductor device according to a third modification, and corresponds to fig. 6. Fig. 22 is a cross-sectional view of a semiconductor device of a fourth modification. Fig. 23 is a cross-sectional view of a semiconductor device of a fourth modification. Fig. 24 is a cross-sectional view of a semiconductor device of a fifth modification. Fig. 25 is a cross-sectional view of a semiconductor device of a fifth modification. Fig. 26 is a cross-sectional view of a semiconductor device according to a sixth modification, and corresponds to fig. 5. Fig. 27 is a cross-sectional view of a semiconductor device according to a sixth modification, and corresponds to fig.