CN-121986569-A - Transistor and method for manufacturing the same

Abstract

A transistor may include a substrate, a drain layer formed within the substrate at a first side of the substrate. The first well implant has a first implant depth, the second well implant has a second implant depth, and the third well implant has a third implant depth. The first well implant, the second well implant, and the third well implant are formed within the substrate at a second side of the substrate. The second implantation depth is greater than the first implantation depth and the third implantation depth is greater than the second implantation depth. The gate is formed at the second side of the substrate. The gate overlaps the first well implant a first distance, the gate overlaps the second well implant a second distance, and the gate overlaps the third well implant a third distance.

Inventors

• S, M, pan di
• R. Yaqi
• B Auden Kirk

Assignees

• 微芯片技术股份有限公司

Dates

Publication Date

20260505

Application Date

20240618

Priority Date

20240607

Claims (16)

1. 1. A transistor, the transistor comprising: A substrate; A drain layer formed within the substrate at a first side of the substrate; A first well implant formed within the substrate at a second side of the substrate, the first well implant having a first implant depth; A second well implant formed within the substrate at the second side of the substrate, the second well implant having a second implant depth, wherein the second implant depth is greater than the first implant depth; A third well implant formed within the substrate at the second side of the substrate, the third well implant having a third implant depth, wherein the third implant depth is greater than the second implant depth, and A gate formed at the second side of the substrate, wherein the gate overlaps the first well implant by a first distance, the gate overlaps the second well implant by a second distance, and the gate overlaps the third well implant by a third distance.
2. 2. The transistor of claim 1, wherein the first distance is greater than the second distance.
3. 3. The transistor of claim 2, wherein the second distance is greater than the third distance.
4. 4. The transistor of claim 1, wherein the substrate comprises a first type of dopant and the first, second, and third well implants comprise a second type of dopant.
5. 5. The transistor of claim 4, wherein the substrate comprises a first concentration of the first type of dopant and the drain layer comprises a second concentration of the first type of dopant.
6. 6. The transistor of claim 5, wherein the second concentration is greater than the first concentration.
7. 7. The transistor of claim 6, wherein the first type of dopant comprises an n-type dopant and the second type of dopant comprises a p-type dopant.
8. 8. The transistor of claim 6, wherein the first type of dopant comprises a p-type dopant and the second type of dopant comprises an n-type dopant.
9. 9. A method of manufacturing a transistor, the method comprising: Providing a substrate; Forming a first well implant within the substrate at a second side of the substrate, the first well implant having a first implant depth; forming a second well implant within the substrate at the second side of the substrate, the second well implant having a second implant depth, wherein the second implant depth is greater than the first implant depth; Forming a third well implant within the substrate at the second side of the substrate, the third well implant having a third implant depth, wherein the third implant depth is greater than the second implant depth, and A gate is formed at the second side of the substrate, wherein the gate overlaps the first well implant a first distance, the gate overlaps the second well implant a second distance, and the gate overlaps the third well implant a third distance.
10. 10. The method of claim 9, wherein the first distance is greater than the second distance.
11. 11. The method of claim 10, wherein the second distance is greater than the third distance.
12. 12. The method of claim 9, wherein the substrate comprises a first type of dopant and the first, second, and third well implants comprise a second type of dopant.
13. 13. The method of claim 12, wherein the substrate comprises a first concentration of the first type of dopant and the drain layer comprises a second concentration of the first type of dopant.
14. 14. The method of claim 13, wherein the second concentration is greater than the first concentration.
15. 15. The method of claim 14, wherein the first type of dopant comprises an n-type dopant and the second type of dopant comprises a p-type dopant.
16. 16. The method of claim 14, wherein the first type of dopant comprises a p-type dopant and the second type of dopant comprises an n-type dopant.

Description

Transistor and method for manufacturing the same Cross Reference to Related Applications The present application claims priority from U.S. provisional patent application No. 63/542,735, filed on 5 th month 10 of 2023, and U.S. non-provisional patent application No. 18/736,957, filed on 7 th 6 of 2024, the contents of which are hereby incorporated by reference in their entireties. Technical Field The present disclosure relates generally to transistors, and more particularly to a stepped channel power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and method of manufacturing the same to reduce the drain-source on-resistance R DS(on) of the transistor. Disclosure of Invention According to one or more exemplary aspects, a transistor may include a substrate, a drain layer formed at a first side of the substrate within the substrate, a first well implant formed at a second side of the substrate within the substrate, the first well implant having a first implant depth, a second well implant formed at a second side of the substrate within the substrate, the second well implant having a second implant depth, wherein the second implant depth is greater than the first implant depth, a third well implant formed at a second side of the substrate within the substrate, the third well implant having a third implant depth, wherein the third implant depth is greater than the second implant depth, and a gate formed at the second side of the substrate, wherein the gate overlaps the first well implant by a first distance, the gate overlaps the second well implant by a second distance, and the gate overlaps the third well implant by a third distance. The first implantation depth may be about 5nm to 50nm. The second implantation depth may be about 10nm to 100nm. The third implantation depth may be about 15nm to 150nm. The first distance may be greater than the second distance. The second distance may be greater than the third distance. The substrate may include a first type dopant and the first, second, and third well implants may include a second type dopant. The substrate may include a first concentration of a first type dopant and the drain layer may include a second concentration of the first type dopant. The second concentration may be greater than the first concentration. The substrate may include a second type dopant and the first, second, and third well implants may include a first type dopant. The substrate may include a first concentration of a second type dopant, and the drain layer may include a second concentration of the second type dopant. The second concentration may be greater than the first concentration. According to one or more exemplary aspects, a method of manufacturing a transistor is provided. The method may include providing a substrate, forming a drain layer within the substrate at a first side of the substrate, forming a first well implant within the substrate at a second side of the substrate, the first well implant having a first implant depth, forming a second well implant within the substrate at the second side of the substrate, the second well implant having a second implant depth, wherein the second implant depth is greater than the first implant depth, forming a third well implant within the substrate at the second side of the substrate, the third well implant having a third implant depth, wherein the third implant depth is greater than the second implant depth, and forming a gate at the second side of the substrate, wherein the gate overlaps the first well implant by a first distance, the gate overlaps the second well implant by a second distance, and the gate overlaps the third well implant by a third distance. The first implantation depth may be about 5nm to 50nm. The second implantation depth may be about 10nm to 100nm. The third implantation depth may be about 15nm to 150nm. The first distance may be greater than the second distance. The second distance may be greater than the third distance. The substrate may include a first type dopant and the first, second, and third well implants may include a second type dopant. The substrate may include a first concentration of a first type dopant and the drain layer may include a second concentration of the first type dopant. The second concentration may be greater than the first concentration. The substrate may include a second type dopant and the first, second, and third well implants may include a first type dopant. The substrate may include a first concentration of a second type dopant, and the drain layer may include a second concentration of the second type dopant. The second concentration may be greater than the first concentration. Drawings Fig. 1 shows a diagram of a transistor according to one or more examples. Fig. 2A is a cross-sectional view of some of the steps in a method of fabricating a transistor according to one or more examples. Fig. 2B is a cross-sectional view of some of the steps in a method of fabricating a transist