Search

CN-121986580-A - Method for forming low-K dielectric materials with reduced dielectric constant and high mechanical strength

CN121986580ACN 121986580 ACN121986580 ACN 121986580ACN-121986580-A

Abstract

An example semiconductor processing method may include providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The first silicon-containing precursor may comprise Si-O bonds. The method may include forming a plasma of the first silicon-containing precursor and the second silicon-containing precursor in the processing region. The method may include forming a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant of less than or about 3.0.

Inventors

  • LU RUI
  • XIE BO
  • ZHAO QIUJING
  • YAO PANPAN
  • LI XIAOBO
  • LANG JIYI
  • XIA LIQUN
  • S. Venkat Raman

Assignees

  • 应用材料公司

Dates

Publication Date
20260505
Application Date
20240819
Priority Date
20230825

Claims (20)

  1. 1. A semiconductor processing method, the semiconductor processing method comprising: providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region of the semiconductor processing chamber, and wherein the first silicon-containing precursor comprises Si-O bonds; forming a plasma of the first and second silicon-containing precursors in the processing region, and A layer of silicon-containing material is formed on the substrate, wherein the layer of silicon-containing material is characterized by a dielectric constant of less than or about 3.0.
  2. 2. The semiconductor processing method of claim 1, wherein the first silicon-containing precursor comprises octamethyl cyclotetrasiloxane, 2,4,6, 8-tetramethyl-2, 4,6, 8-tetravinyl cyclotetrasiloxane, 2,4,6, 8-tetramethyl cyclotetrasiloxane, dimethyldimethoxy silane, ethoxydimethyl silane, isobutylmethyl dimethoxy silane, vinylmethyl dimethoxy silane, 1, 3-tetramethyl-1, 3-dimethoxy disiloxane, 1, 3-dimethyl-1, 3-tetramethoxy disiloxane, methoxy (dimethyl) silane-based methane, methyl (dimethoxy) silane-based methane, bis (trimethylsilyl) methane, bis (methyldimethoxy silane-based) methane, bis (dimethylmethoxy silane-based) methane, 1, 3-diethoxy-1, 3-dimethyl-1, 3-disilacyclobutane, 1, 3-tetramethyl-1, 3-disilacyclobutane, or 1, 3-dimethyl-1, 3-disilacyclobutane.
  3. 3. The semiconductor processing method of claim 1, wherein the first silicon-containing precursor is dimethyldimethoxy silane and the second silicon-containing precursor is 1, 3-diethoxy-1, 3-dimethyl-1, 3-disilacyclobutane.
  4. 4. The semiconductor processing method of claim 1, wherein a flow ratio of the first silicon-containing precursor to the second silicon-containing precursor is greater than or about 1:1.
  5. 5. The semiconductor processing method of claim 1, further comprising: an oxygen-containing precursor is provided to the processing region of the semiconductor processing chamber along with the first silicon-containing precursor and the second silicon-containing precursor.
  6. 6. The semiconductor processing method of claim 1, wherein the temperature within the semiconductor processing chamber is maintained at less than or about 450 ℃ while the layer of silicon-containing material is formed on the substrate.
  7. 7. The semiconductor processing method of claim 1, wherein the pressure within the semiconductor processing chamber is maintained at less than or about 500 torr while the layer of silicon-containing material is formed on the substrate.
  8. 8. The semiconductor processing method of claim 1, wherein said silicon-containing material layer is characterized by a hardness of greater than or about 3.5 GPa.
  9. 9. The semiconductor processing method of claim 1, wherein said silicon-containing material layer is characterized by a dielectric constant of less than or about 2.8.
  10. 10. The semiconductor processing method of claim 1, further comprising: The layer of silicon-containing material on the substrate is hardened by directing Ultraviolet (UV) energy toward the substrate.
  11. 11. The semiconductor processing method of claim 10, wherein the hardening comprises providing helium-containing material, argon-containing material, or both to the processing region of the semiconductor processing chamber at a temperature between about 75 ℃ and about 400 ℃ and at a pressure between about 3 torr and about 100 torr.
  12. 12. A semiconductor processing method, the semiconductor processing method comprising: providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region of the semiconductor processing chamber, and wherein the first silicon-containing precursor comprises Si-O bonds; forming a plasma of the first silicon-containing precursor and the second silicon-containing precursor in the processing region; Forming a layer of silicon-containing material on the substrate, wherein the layer of silicon-containing material is characterized by a dielectric constant of less than or about 3.0, and The layer of silicon-containing material on the substrate is hardened by directing Ultraviolet (UV) energy toward the substrate.
  13. 13. The semiconductor processing method of claim 12, further comprising: Diatomic oxygen (O 2 ) is provided to the processing region of the semiconductor processing chamber along with the first silicon-containing precursor and the second silicon-containing precursor.
  14. 14. The semiconductor processing method of claim 12, wherein the plasma of the first and second silicon-containing precursors is formed at less than or about 1,500W.
  15. 15. The semiconductor processing method of claim 12, wherein hardening the layer of silicon-containing material on the substrate comprises directing a first UV energy toward the substrate for a first period of time and directing a second UV energy toward the substrate for a second period of time, wherein the first UV energy and the second UV energy are characterized by different wavelengths.
  16. 16. The semiconductor processing method of claim 12, wherein methyl incorporation (methyl incorporation) in said silicon-containing material layer on said substrate is greater than or about 1.5%.
  17. 17. The semiconductor processing method of claim 12, wherein said silicon-containing material layer is characterized by a young's modulus of greater than or about 15.0 MPa.
  18. 18. A semiconductor processing method, the semiconductor processing method comprising: providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region of the semiconductor processing chamber, and wherein the first silicon-containing precursor comprises Si-O bonds; forming a plasma of the first silicon-containing precursor and the second silicon-containing precursor in the processing region; Forming a layer of silicon-containing material on the substrate, wherein the layer of silicon-containing material is characterized by a hardness of greater than or about 3.5 GPa, and The layer of silicon-containing material on the substrate is hardened by directing Ultraviolet (UV) energy toward the substrate.
  19. 19. The semiconductor processing method of claim 18, wherein the first silicon-containing precursor comprises octamethyl cyclotetrasiloxane, 2,4,6, 8-tetramethyl-2, 4,6, 8-tetravinyl cyclotetrasiloxane, 2,4,6, 8-tetramethyl cyclotetrasiloxane, dimethyldimethoxy silane, ethoxydimethyl silane, isobutylmethyl dimethoxy silane, vinylmethyl dimethoxy silane, 1, 3-tetramethyl-1, 3-dimethoxy disiloxane, 1, 3-dimethyl-1, 3-tetramethoxy disiloxane, methoxy (dimethyl) silane-based methane, methyl (dimethoxy) silane-based methane, bis (trimethylsilyl) methane, bis (methyldimethoxy silane-based) methane, bis (dimethylmethoxy silane-based) methane, 1, 3-diethoxy-1, 3-dimethyl-1, 3-disilacyclobutane, 1, 3-tetramethyl-1, 3-disilacyclobutane, or 1, 3-dimethyl-1, 3-disilacyclobutane.
  20. 20. The semiconductor processing method of claim 18, wherein the silicon-containing material layer is characterized by a dielectric constant of less than or about 2.8, and wherein the silicon-containing material layer is characterized by a hardness of greater than or about 4.5 GPa.

Description

Method for forming low-K dielectric materials with reduced dielectric constant and high mechanical strength Technical Field This application request 2023, 8, 25, claims priority from U.S. patent application Ser. No. 18/238,107, entitled "METHODS FOR FORMING LOW-K DIELECTRIC MATERIALS WITH REDUCED DIELECTRIC CONSTANT AND HIGH MECHANICAL STRENGTH", incorporated herein by reference in its entirety. The present technology relates to deposition processes and chambers. More particularly, the present technology relates to methods of forming low-k materials. Background Integrated circuits can be fabricated by a process that produces intricate patterned material layers on the substrate surface. Creating patterned material on a substrate requires a controlled method for forming and removing the material. Material properties may affect the operation of the device and may also affect the manner in which the films are removed relative to one another. Plasma enhanced deposition can produce films with certain characteristics. In order to provide suitable properties, the formation of many films requires additional processing to adjust or enhance the material properties of the film. Accordingly, there is a need for improved systems and methods that can be used to produce high quality components and structures. These and other needs are met by the present technology. Disclosure of Invention An example semiconductor processing method may include providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber. The substrate may be disposed within a processing region of a semiconductor processing chamber. The first silicon-containing precursor may comprise Si-O bonds. The method may include forming a plasma of a first silicon-containing precursor and a second silicon-containing precursor in a processing region. The method may include forming a layer of silicon-containing material on a substrate. The layer of silicon-containing material may be characterized by a dielectric constant of less than or about 3.0. In some embodiments, the first silicon-containing precursor may be or may include: octamethyl cyclotetrasiloxane, 2,4,6, 8-tetramethyl-2, 4,6, 8-tetravinyl cyclotetrasiloxane, 2,4,6, 8-tetramethyl cyclotetrasiloxane, dimethyl dimethoxy silane, ethoxy dimethyl silane, isobutyl methyl dimethoxy silane, vinyl methyl dimethoxy silane, 1, 3-tetramethyl-1, 3-dimethoxy disiloxane, 1, 3-dimethyl-1, 3-tetramethoxy disiloxane methoxy (dimethyl) silane-based methane, methyl (dimethoxy) silane-based methane, bis (trisilyl) methane, bis (methyldimethoxysilane-based) methane, bis (dimethylmethoxysilane-based) methane, 1, 3-diethoxy-1, 3-dimethyl-1, 3-disilacyclobutane, 1, 3-tetramethyl-1, 3-disilacyclobutane, or 1, 3-dimethyl-1, 3-diphenyl-1, 3-disilacyclobutane. The first silicon-containing precursor may be dimethyldimethoxysilane and the second silicon-containing precursor may be 1, 3-diethoxy-1, 3-dimethyl-1, 3-disilacyclobutane. The ratio of flow rates of the first silicon-containing precursor to the second silicon-containing precursor may be greater than or about 1:1. The method may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber along with a first silicon-containing precursor and a second silicon-containing precursor. When forming a layer of silicon-containing material on a substrate, the temperature within the semiconductor processing chamber may be maintained at less than or about 450 ℃. When forming a layer of silicon-containing material on a substrate, the pressure within the semiconductor processing chamber may be maintained at less than or about 500 torr. The layer of silicon-containing material may be characterized by a hardness of greater than or about 3.5 GPa. The layer of silicon-containing material may be characterized by a dielectric constant of less than or about 2.8. The method may include hardening a silicon-containing material layer on a substrate by directing Ultraviolet (UV) energy toward the substrate. Hardening may include providing helium-containing material, argon-containing material, or both to a processing region of a semiconductor processing chamber at a temperature between about 75 ℃ and about 400 ℃ and at a pressure between about 3 torr and about 100 torr. Some embodiments of the present technology may cover semiconductor processing methods. The method may include providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber. The substrate may be disposed within a processing region of a semiconductor processing chamber. The first silicon-containing precursor may comprise Si-O bonds. The method may include forming a plasma of a first silicon-containing precursor and a second silicon-containing precursor in a processing region. The method may include forming a layer of silicon