CN-121986591-A - Die backside profile for semiconductor devices

Abstract

Embodiments of the present disclosure include apparatus and methods of forming backside profiles in semiconductor elements that include die-to-wafer bonding. The method generally includes removing a portion of a substrate layer included in a plurality of dies arranged on and bonding an insulating layer included in a support structure, wherein the plurality of dies define a plurality of channels between adjacent dies, and forming corner features on a plurality of corners of the substrate layer adjacent to the plurality of channels. The use of backside profiles as described herein may mitigate downstream process risks associated with trapped residues in the channels and provide stress relief for the semiconductor elements.

Inventors

• Lin Yinwei
• XU YUANHUI
• LONG CHANGFAN
• Prayuti Liantuo
• Alvin sandrayan
• SUN CHENG

Assignees

• 应用材料公司

Dates

Publication Date

20260505

Application Date

20240716

Priority Date

20230816

Claims (20)

1. 1. A method, the method comprising: Removing a portion of a substrate layer included in a plurality of dies arranged on and bonding an insulating layer included in a support structure, wherein the plurality of dies define a plurality of channels between adjacent dies, and Corner features are formed on a plurality of corners of the substrate layer adjacent to the plurality of channels.
2. 2. The method of claim 1, wherein at least one sidewall of at least one die of the plurality of dies is tapered, and wherein an angle of the at least one tapered sidewall is between 60 degrees and 85 degrees.
3. 3. The method of claim 1, wherein the corner feature has a radius between 5 micrometers (μιη) and 20 μιη.
4. 4. The method of claim 1, wherein the angle of the corner feature is between 5 degrees and 45 degrees.
5. 5. The method of claim 1, wherein a distance between sidewalls of the plurality of dies and global interconnects included in the plurality of dies and the support structure is at least 10 micrometers (μιη), and wherein the corner feature is disposed between the sidewalls and the global interconnects.
6. 6. The method of claim 1, wherein a length of the plurality of channels from a top of the corner feature on a first die of the plurality of dies to a top of the corner feature on a second die of the plurality of dies is between 50 micrometers (μιη) and 4 millimeters (mm).
7. 7. The method of claim 1, the method further comprising: the substrate layer is planarized by a chemical mechanical planarization process.
8. 8. The method of claim 1, wherein forming the corner features on the plurality of corners comprises etching the corner features by a first Reactive Ion Etching (RIE) process.
9. 9. The method of claim 8, wherein the first RIE process comprises using at least one of sulfur hexafluoride (SF 6 ), oxygen (O 2 ), trifluoromethane (CHF 3 ), octafluorocyclobutane (C 4 F 8 ), or fluorinated methane (CH 3 F).
10. 10. The method of claim 9, wherein the first RIE process comprises using a radio frequency between 400 kilohertz (KHz) and 14 megahertz (MHz), an RF power of less than 7 kilowatts (kW), a flow rate of less than 2000 standard cubic centimeters per minute (sccm), and a pressure between 20 millitorr (mT) and 250mT for less than 5 minutes.
11. 11. The method of claim 10, wherein removing the portion of the substrate layer included in the plurality of dies comprises etching the portion of the substrate layer by a second RIE process.
12. 12. The method of claim 11, wherein the second RIE process has a selectivity ratio between the substrate layer and the insulating layer of at least 100:1.
13. 13. The method of claim 12, wherein the second RIE process comprises using at least one of SF 6 、CH 3 F, or C 4 F 8 .
14. 14. The method of claim 13, wherein the second RIE process comprises using a radio frequency between 400 kilohertz (KHz) and 14 megahertz (MHz), an RF power of less than 7 kilowatts (kW), a flow rate of less than 2000 standard cubic centimeters per minute (sccm), and a pressure between 20 millitorr (mT) and 80mT for less than 10 minutes.
15. 15. An interconnect structure, the interconnect structure comprising: a support structure comprising an insulating layer; a plurality of dies arranged on and bonded to the insulating layer, wherein the plurality of dies comprise a substrate layer, and wherein the plurality of dies define a plurality of channels between adjacent dies, and Corner features included on a plurality of corners of the substrate layer and adjacent to the plurality of channels.
16. 16. The interconnect structure of claim 15, wherein at least one sidewall of at least one die of the plurality of dies is tapered, and wherein an angle of the at least one tapered sidewall is between 60 degrees and 85 degrees.
17. 17. The interconnect structure of claim 15, wherein the corner feature has a radius between 5 micrometers (μιη) and 20 μιη.
18. 18. The interconnect structure of claim 15, wherein the angle of the corner feature is between 5 degrees and 45 degrees.
19. 19. An interconnect structure, the interconnect structure comprising: a support structure including an insulating layer, and A plurality of dies arranged on and bonded to the insulating layer, wherein the plurality of dies comprises a substrate layer, wherein the plurality of dies define a plurality of channels between adjacent dies, and wherein at least one sidewall of at least one die of the plurality of dies is tapered.
20. 20. The interconnect structure of claim 15, the interconnect structure further comprising: corner features included on a plurality of corners of the substrate layer and adjacent to the plurality of channels.

Description

Die backside profile for semiconductor devices Technical Field Embodiments described herein relate generally to semiconductor device fabrication. More particularly, embodiments of the present disclosure relate to semiconductor devices with die-to-wafer bonding, including backside profiles, and methods of forming the same. Background Bonding of dice (e.g., semiconductor chips) to a wafer (e.g., substrate) may result in gaps between adjacent dice on the wafer. These gaps may be referred to as inter-die (inter-die) spacing. With the advancement of semiconductor device technology, the length of inter-die spacing has been continuously reduced. Current die-to-wafer bonding typically results in inter-die spacing of 100 micrometers (μm) or less. However, as the inter-grain spacing decreases, the risk of trapped residues in the inter-grain spacing increases. The trapped residues often create a variety of problems during semiconductor device fabrication, including challenges and risks in downstream processes. Accordingly, there is a need in the art for a variety of methods and apparatus to address the above-described problems. Disclosure of Invention To the accomplishment of the foregoing and related ends, one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed. Embodiments of the present disclosure provide a method. The method generally includes removing a portion of a substrate layer included in a plurality of dies. A plurality of dies are arranged on an insulating layer included in the support structure and bond the insulating layer. The plurality of dies define a plurality of channels between adjacent dies. The method also generally includes forming corner features on a plurality of corners of the substrate layer adjacent the plurality of channels. Embodiments of the present disclosure provide an interconnect structure. The interconnect structure generally includes a support structure including an insulating layer and a plurality of dies arranged on and bonded to the insulating layer. The plurality of dies includes a substrate layer, and the plurality of dies define a plurality of channels between adjacent dies. The interconnect structure also generally includes corner features included on a plurality of corners of the substrate layer adjacent the plurality of channels. The embodiment of the invention provides an interconnection structure. The interconnect structure generally includes a support structure including an insulating layer, and a plurality of dies arranged on and bonded to the insulating layer. The plurality of dies includes a substrate layer. The plurality of dies also define a plurality of channels between adjacent dies, and at least one sidewall of the plurality of dies is tapered. Embodiments of the present disclosure provide a semiconductor element with die-to-wafer bonding that includes a backside profile as described herein. Drawings So that the manner in which the above recited features of embodiments of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. Fig. 1A illustrates a top view of a portion of a semiconductor component having die-to-wafer bonding in which embodiments of the present disclosure may be implemented. Fig. 1B shows a cross-sectional view taken along section line 1B in fig. 1A, in which embodiments of the present disclosure may be implemented. Fig. 2 is a flow chart of a method of forming a backside profile on a semiconductor element including die-to-wafer bonding, in accordance with one or more embodiments described herein. Fig. 3A, 3B, 3C, and 3D illustrate schematic side cross-sectional views of a portion of a semiconductor element during formation according to one or more embodiments described herein. To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. Detailed Description Embodiments of the present disclosure generally relate to semiconductor devices having die-to-wafer bonding and methods of forming the same, including backside profiles. The semiconductor device may include a plurality of dies bonded to a support str