CN-121986595-A - Line Edge Roughness (LER) improvement of resist pattern

Abstract

An exemplary semiconductor processing method may include a substrate housed in a processing region. A layer of silicon-containing material may be disposed on the substrate, a patterned resist material may be disposed on the layer of silicon-containing material, and a layer of carbon-containing material may be disposed on the patterned resist material and the layer of silicon-containing material. The method may include providing a hydrogen-containing precursor, a nitrogen-containing precursor, or both to a processing region of a semiconductor processing chamber, forming a plasma effluent of a hydrogen-containing precursor and/or a nitrogen-containing precursor, and contacting the substrate with the plasma effluent of the hydrogen-containing precursor and/or the nitrogen-containing precursor. The contacting may remove a portion of the layer of carbonaceous material. The method may include providing a fluorine-containing precursor to the processing region, forming a plasma effluent of the fluorine-containing precursor, and contacting the substrate with the plasma effluent of the fluorine-containing precursor.

Inventors

• S. D. Sherpa
• A. Lanjian

Assignees

• 应用材料公司

Dates

Publication Date

20260505

Application Date

20240926

Priority Date

20231003

Claims (20)

1. 1. A semiconductor processing method, the semiconductor processing method comprising: Providing a carbon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is received in the processing region, wherein a layer of silicon-containing material is disposed on the substrate, and wherein a patterned resist material is disposed on the layer of silicon-containing material; Contacting the substrate with the carbon-containing precursor, wherein the contacting deposits a layer of carbon-containing material on the substrate; Providing a hydrogen-containing precursor, a nitrogen-containing precursor, and both to the processing region; forming a plasma effluent of the hydrogen-containing precursor and/or the nitrogen-containing precursor; Contacting the substrate with the plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor, wherein the contacting etches a portion of the layer of carbon-containing material to expose a portion of the layer of silicon-containing material; Providing a fluorine-containing precursor to the treatment zone; forming a plasma effluent of the fluorine-containing precursor, and Contacting the substrate with the plasma effluent of the fluorine-containing precursor, wherein the contacting etches features in the silicon-containing material layer, and wherein a semiconductor processing chamber operating temperature is maintained at less than or about 0 ℃.
2. 2. The semiconductor processing method of claim 1, wherein the silicon-containing material layer comprises a silicon-containing oxygen and nitrogen material or a silicon anti-reflective coating (SiARC).
3. 3. The semiconductor processing method of claim 1, wherein said layer of carbon-containing material is characterized by a thickness of less than or about 10 nm a.
4. 4. The semiconductor processing method of claim 1, wherein the hydrogen-containing precursor comprises diatomic hydrogen (H 2 ).
5. 5. The semiconductor processing method of claim 1, wherein the nitrogen-containing precursor comprises diatomic nitrogen (N 2 ).
6. 6. The semiconductor processing method of claim 1, wherein the fluorine-containing precursor comprises Hydrogen Fluoride (HF).
7. 7. The semiconductor processing method of claim 1, wherein said plasma effluent of said fluorine-containing precursor is formed at a plasma power of less than or about 500W.
8. 8. The semiconductor processing method of claim 1, further comprising: a bias voltage is applied while contacting the substrate with the plasma effluent of the fluorine-containing precursor.
9. 9. The semiconductor processing method of claim 8, wherein the bias voltage is less than or about 1.2 kV.
10. 10. The semiconductor processing method of claim 1, wherein the silicon-containing material layer is characterized by a Line Edge Roughness (LER) of less than or about 2 nm.
11. 11. The semiconductor processing method of claim 1, wherein the semiconductor processing chamber operating pressure is less than or about 100 mTorr.
12. 12. A semiconductor processing method, the semiconductor processing method comprising: Providing a hydrogen-containing precursor, a nitrogen-containing precursor, or both to a processing region of a semiconductor processing chamber, wherein a substrate is received in the processing region, wherein a layer of silicon-containing material is disposed on the substrate, wherein a patterned resist material is disposed on the layer of silicon-containing material, and wherein a layer of carbon-containing material is disposed on the patterned resist material and the layer of silicon-containing material; forming a plasma effluent of the hydrogen-containing precursor and/or the nitrogen-containing precursor; Contacting the substrate with the plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor, wherein the contacting etches a portion of the layer of carbon-containing material to expose a portion of the layer of silicon-containing material; Providing a fluorine-containing precursor to the treatment zone; forming a plasma effluent of the fluorine-containing precursor, and Contacting the substrate with the plasma effluent of the fluorine-containing precursor, wherein the contacting etches features in the silicon-containing material layer, and wherein the carbon-containing material layer is characterized by a Line Edge Roughness (LER) of less than or about 1.5 nm.
13. 13. The semiconductor processing method of claim 12, wherein the substrate further comprises a bottom antireflective coating (BARC) material layer disposed between the silicon-containing material layer and the patterned resist material.
14. 14. The semiconductor processing method of claim 12, further comprising: The plasma power is pulsed as plasma effluents of the fluorine-containing precursor are formed.
15. 15. The semiconductor processing method of claim 14, wherein the plasma power is pulsed at a duty cycle of less than or about 90%.
16. 16. The semiconductor processing method of claim 12, wherein the semiconductor processing chamber operating temperature is maintained at less than or about-40 ℃.
17. 17. A semiconductor processing method, the semiconductor processing method comprising: Providing a carbon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is received in the processing region, wherein a layer of silicon-containing material is disposed on the substrate, wherein a layer of bottom antireflective coating (BARC) material is disposed on the layer of silicon-containing material, wherein a patterned resist material is disposed on the layer of BARC material, and wherein sidewalls of the patterned resist material are characterized by a Line Edge Roughness (LER) of greater than or about 2 nm; Contacting the substrate with the carbon-containing precursor, wherein the contacting deposits a layer of carbon-containing material on the substrate; Providing a hydrogen-containing precursor, a nitrogen-containing precursor, and both to the processing region; forming a plasma effluent of the hydrogen-containing precursor and/or the nitrogen-containing precursor; Contacting the substrate with the plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor, wherein the contacting etches a portion of the layer of carbon-containing material to expose a portion of the layer of silicon-containing material; Providing a fluorine-containing precursor to the processing region, wherein the fluorine-containing precursor comprises Hydrogen Fluoride (HF); forming a plasma effluent of the fluorine-containing precursor, and Contacting the substrate with the plasma effluent of the fluorine-containing precursor, wherein the contacting etches features in the silicon-containing material layer, and wherein a semiconductor processing chamber operating temperature is maintained at less than or about 0 ℃.
18. 18. The semiconductor processing method of claim 17, wherein said plasma effluent of said fluorine-containing precursor is formed at a plasma power of less than or about 500W.
19. 19. The semiconductor processing method of claim 17, wherein contacting the substrate with the carbon-containing precursor reduces the LER of the patterned resist material.
20. 20. The semiconductor processing method of claim 17, wherein contacting the substrate with the plasma effluent of the fluorine-containing precursor etches the silicon-containing material layer and the BARC material layer selectively relative to the patterned resist material.

Description

Line Edge Roughness (LER) improvement of resist pattern Technical Field The present application claims the benefit and priority of U.S. patent application Ser. No. 18/376,053, entitled "LINE EDGE ROUGHNESS (LER) IMPROVEMENT OF RESIST PATTERNS," filed on even 3, month 10, 2023, the entire contents of which are incorporated herein by reference. The present technology relates to semiconductor processes and apparatus. More particularly, the present technology relates to improving line edge roughness prior to etching operations. Background Integrated circuits may be fabricated by a process that produces a complex patterned layer of material on the substrate surface. Creating patterned material on a substrate requires a controlled method for removing the exposed material. Chemical etching is used for various purposes, including transferring a pattern in the photoresist into an underlying layer, thinning the layer, or thinning the lateral dimensions of features already present on the surface. It is often desirable to have an etching process that etches one material faster than another material, thereby facilitating, for example, a pattern transfer process. Such an etching process is believed to be selective to the first material. Due to the variety of materials, circuits, and processes, etching processes have been developed that are selective to a variety of materials. The etching process may be referred to as wet or dry based on the materials used in the process. Wet HF etches preferentially etch silicon oxide over other dielectrics and materials. However, wet processes may have difficulty penetrating some limited trenches and sometimes may also deform the remaining material. The dry etch generated in the localized plasma formed within the substrate processing region may penetrate the more confined trenches and exhibit less deformation of the fragile residual structure. However, the localized plasma may damage the substrate due to arcing during discharge. Accordingly, there is a need for improved systems and methods that can be used to produce high quality components and structures. These and other needs are addressed by the present technology. Disclosure of Invention An exemplary semiconductor processing method may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. The substrate may be accommodated in the processing region. A layer of silicon-containing material may be disposed on the substrate. A patterned resist material may be disposed on the layer of silicon-containing material. The method may include contacting the substrate with a carbon-containing precursor. The contact may deposit a layer of carbonaceous material on the substrate. The method can include providing a hydrogen-containing precursor, a nitrogen-containing precursor, and both to a processing region. The method may include forming a plasma effluent of a hydrogen-containing precursor and/or a nitrogen-containing precursor. The method may include contacting the substrate with plasma effluents of a hydrogen-containing precursor and/or a nitrogen-containing precursor. A portion of the etchable carbon-containing material layer is contacted to expose a portion of the silicon-containing material layer. The method may include providing a fluorine-containing precursor to the processing region. The method may include forming a plasma effluent of a fluorine-containing precursor. The method may include contacting the substrate with a plasma effluent of a fluorine-containing precursor. Contacts may etch features in the silicon-containing material layer. The semiconductor processing chamber operating temperature may be maintained below or about 0 ℃. In some embodiments, the silicon-containing material layer may be or include a silicon-containing and nitrogen-containing material or a silicon anti-reflective coating (SiARC). The layer of carbonaceous material may be characterized by a thickness of less than or about 10 nm a. The hydrogen-containing precursor may be or include diatomic hydrogen (H 2). The nitrogen-containing precursor may be or include diatomic nitrogen (N 2). The fluorine-containing precursor may be or include Hydrogen Fluoride (HF). The plasma effluent of the fluorine-containing precursor may be formed at a plasma power of less than or about 500W a. The method may include applying a bias voltage while contacting the substrate with plasma effluent of the fluorine-containing precursor. The bias voltage may be less than or about 1.2 kV. The layer of carbonaceous material may be characterized by a line edge roughness (line edge roughness, LER) of less than or about 2 nm. The semiconductor processing chamber operating temperature may be less than or about 100 mTorr a. Some embodiments of the present technology may cover semiconductor processing methods. The method may include providing a hydrogen-containing precursor, a nitrogen-containing precursor, and both to a processing region of a se