CN-121986605-A - Tamper sensor for 3-dimensional die stacking

Abstract

Integrated circuit die stacks capable of detecting physical tampering events and methods thereof are described herein. The integrated circuit die stack includes a first integrated circuit die including a sensor network extending across substantially an entire top surface of the first integrated circuit die and a second integrated circuit die stacked under the first integrated circuit die. The second integrated circuit die is configured to receive the sense signals generated by the sensor network via a plurality of through silicon vias coupled to the first integrated circuit die and the second integrated circuit die.

Inventors

• T. P. Lebuff
• J. ANDERSON
• J. D. Weser Camper
• J.J. MOORE

Assignees

• 赛灵思公司

Dates

Publication Date

20260505

Application Date

20240830

Priority Date

20230928

Claims (15)

1. 1. An integrated circuit die stack, the integrated circuit die stack comprising: A first integrated circuit die including a sensor network extending across substantially an entire top surface of the first integrated circuit die, and A second integrated circuit die stacked under the first integrated circuit die and configured to receive the sense signals generated by the sensor network via a plurality of through silicon vias coupled with the first and second integrated circuit die.
2. 2. The integrated circuit die stack of claim 1, wherein the sensor network comprises a plurality of addressable memory banks arranged across a layer parallel to a plane of a top surface of the first integrated circuit die.
3. 3. The integrated circuit die stack of claim 2, wherein the plurality of addressable memory banks are arranged in an array and the addressable memory banks in the same row or column are connected in series.
4. 4. The integrated circuit die stack of claim 2, wherein at least one of the plurality of addressable memory banks comprises a plurality of shift registers.
5. 5. The integrated circuit die stack of claim 4, wherein the plurality of shift registers are connected in parallel.
6. 6. The integrated circuit die stack of claim 5, wherein each shift register comprises a plurality of flip-flops connected in series.
7. 7. The integrated circuit die stack of claim 6, wherein each shift register comprises a first input operable to receive a clock signal, a second input operable to receive a data signal, a third input operable to receive an activation signal, and a tri-state buffer coupled with the activation signal.
8. 8. The integrated circuit die stack of claim 1, further comprising a third integrated circuit die disposed between the first integrated circuit die and the second integrated circuit die.
9. 9. The integrated circuit die stack of claim 8, wherein the plurality of through silicon vias are coupled with the third integrated circuit die.
10. 10. The integrated circuit die stack of claim 1, wherein the first integrated circuit die further comprises a first read circuit disposed in a first peripheral region of the first integrated circuit die.
11. 11. The integrated circuit die stack of claim 10, wherein the second integrated circuit die further comprises a second read circuit disposed in a second peripheral region of the second integrated circuit die.
12. 12. The integrated circuit die stack of claim 11, wherein the first read circuit and the second read circuit are coupled with the plurality of through silicon vias.
13. 13. The integrated circuit die stack of claim 10, wherein the first read circuit is configured to read the sensor network along one direction.
14. 14. The integrated circuit die stack of claim 13, wherein the first read circuit is configured to read the sensor network in two opposite directions.
15. 15. A method for detecting a tamper event of an integrated circuit die stack, the method comprising: Transmitting probe signals from a second integrated circuit die to a sensor network disposed in a first integrated circuit die, the first integrated circuit die including an input/output interface disposed about a peripheral region of the first integrated circuit die; Routing the probe signals through a plurality of addressable memory banks of the sensor network; Reading, by the input/output interface, sense signals output by the plurality of addressable memory banks generated based on the sense signals, and The sense signal is provided to the second integrated circuit die via a plurality of through silicon vias, the second integrated circuit die stacked under the first integrated circuit die and configured to determine the tamper event based on the sense signal.

Description

Tamper sensor for 3-dimensional die stacking Technical Field Embodiments of the present invention relate generally to integrated circuit die stacks capable of sensing a tamper event and, in particular, to integrated circuit die stacks that utilize a network of addressable memories to sense a tamper event. Background Electronic devices such as tablet devices, computers, copiers, digital cameras, smart phones, control systems, and automated teller machines often utilize chip package assemblies to add functionality. To increase processing power, chip packaging schemes typically form a die stack by vertically mounting a plurality of integrated circuit dies to a package substrate. These integrated circuit die stacks may include storage, logic, communication, power management, or other functions. Recently, physical attacks have been tested to gain access to internal data and algorithms of stacked integrated circuit dies. These physical attacks utilize backside access to perform laser attacks, focused ion beam attacks, and other tampering activities. Such tamper attempts typically require physical access. At the same time, recent developments in chips with thinner substrates and active-on-active stacked die architectures have added more challenges to thwart the above-described physical attacks. Accordingly, there is a need for an integrated circuit die stack with improved security. Disclosure of Invention Integrated circuit die stacks capable of detecting physical tampering events and methods thereof are described herein. The integrated circuit die stack includes a first integrated circuit die including a sensor network extending across substantially an entire top surface of the first integrated circuit die and a second integrated circuit die stacked under the first integrated circuit die. The second integrated circuit die is configured to receive the sense signals generated by the sensor network via a plurality of through silicon vias coupled to the first integrated circuit die and the second integrated circuit die. The method includes inputting a probe signal from a second integrated circuit die to a sensor network disposed on a first integrated circuit die, the first integrated circuit die including an input/output interface disposed around a peripheral region of the first integrated circuit die, injecting the probe signal through a plurality of addressable memories of the sensor network, reading, by the input/output interface, a sense signal based on the probe signal output by the plurality of addressable memories, and providing the sense signal to the second integrated circuit die via a plurality of through-silicon vias, the second integrated circuit die stacked under the first integrated circuit die and configured to determine a tamper event based on the sense signal. Drawings So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. Fig. 1 is a schematic cross-sectional view of an integrated chip package with stacked integrated circuit dies according to an embodiment. Fig. 2a is a schematic diagram of functional blocks of a top integrated circuit die with a sensor network according to an embodiment. Fig. 2b is a schematic diagram of functional blocks of a bottom integrated circuit die with a sensor network according to an embodiment. Fig. 3 is a schematic circuit diagram of an addressable memory of a sensor network according to an embodiment. Fig. 4a is a schematic signal path of a top integrated circuit die according to an embodiment. Fig. 4b is another illustrative signal path of a top integrated circuit die according to an embodiment. Fig. 5 is a schematic diagram of a reconfiguration sensor network for a top integrated circuit die according to an embodiment. Fig. 6 is a flowchart of a method for sensing a tamper event of an integrated circuit die stack, according to an embodiment. Fig. 7 a-7 c illustrate data created by various operations and stored in a memory of a top integrated circuit die, according to an embodiment. Fig. 8 a-8 f illustrate data created by various operations and stored in a memory of a top integrated circuit die, according to an embodiment. To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments. Detailed Description An Integrated Circuit (IC) die stack is disclosed herein that is capable of detecting a physical attack designed to g