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CN-121988755-A - Lattice structure manufacturability evaluation method based on processing path

CN121988755ACN 121988755 ACN121988755 ACN 121988755ACN-121988755-A

Abstract

The invention relates to a dot matrix structure manufacturability evaluation method based on a processing path, which is used for generating a processing path model of dot matrix cells based on parameters of the dot matrix cells, wherein the processing path model comprises a plurality of layers of processing paths, sequentially carrying out constraint I, constraint II and/or constraint III on each processing path, directly carrying out manufacturability evaluation on the dot matrix cells based on the processing paths on the premise of not depending on a geometric model, and carrying out the evaluation process on the manufacturability evaluation on the dot matrix cells. The method can efficiently and accurately predict the manufacturability of the lattice structure, and is particularly suitable for the prediction evaluation before the manufacture of the large-scale micro lattice structure with a huge amount of fine units.

Inventors

  • TAN SHUJIE
  • DING LIPING
  • Zhang Yicha

Assignees

  • 浙江瑞闻增材技术有限公司

Dates

Publication Date
20260508
Application Date
20260117

Claims (10)

  1. 1. A method for evaluating manufacturability of lattice structure based on processing path is characterized by generating a processing path model of lattice cells based on parameters of the lattice cells, wherein the processing path model comprises a plurality of layers of processing paths, and executing the following operations on the plurality of layers of processing paths: sequentially carrying out constraint one, constraint two and/or constraint three on each processing path, and obtaining the grade of the corresponding processing path: Constraint one, wherein the wall thickness of the lattice unit cells is not smaller than the minimum value of the width of the processing path; constraint two, the processing path of the n+1th layer is contained in a constraint domain defined by the processing path of the n th layer; constraint III, the free length of the processing path is not more than the preset maximum allowed free length; And synthesizing manufacturability grades of the lattice unit cells by integrating all the processing path grades.
  2. 2. The method for evaluating manufacturability of lattice structure based on processing paths of claim 1, wherein a hierarchical processing path evaluation mechanism is established to evaluate the level of each layer of processing paths, the hierarchical processing path evaluation mechanism is as follows: If the constraint I is met, the grade of the processing path of the corresponding layer is 3, if the constraint II is met, otherwise, the grade of the processing path of the corresponding layer is 2, and if the constraint III is met, the grade of the processing path of the corresponding layer is 1; If constraint one is not satisfied, the grade of the processing path of the corresponding layer is 1.
  3. 3. A method for evaluating manufacturability of lattice structures based on processing paths, as set forth in claim 1 or 2, wherein in constraint one, a wall thickness t function of the lattice cells is constructed, ; In order to be the size of the cells, Relative area fraction/volume fraction of cells In the time-course of which the first and second contact surfaces, The minimum value of the machining path width is evaluated as meeting constraint one.
  4. 4. A process-path-based lattice structure manufacturability evaluation method according to claim 1 or 2, wherein in constraint II, when the process path of the n+1th layer Contained in a constraint domain defined by an nth layer processing path When, it is evaluated that constraint two is satisfied, namely: ; wherein the constraint domain From the formula The definition of the term "a" or "an" is, The processing path constraint area of the n+1th layer is obtained by taking boolean as m constraint areas defined by m processing paths of the n-th layer.
  5. 5. The method for evaluating manufacturability of lattice structure based on processing path according to claim 4, wherein the processing path of the (n+1) -th layer Falling at a distance from the nth layer of processing path In the region of (2), the expression is: ; Wherein, the As a function of the distance, Representing the processing path of the ith on the nth layer; Is the maximum distance between the center line of the n+1th layer molten pool and the center line of the n layer molten pool, , In order to print the layer thickness, Is the maximum overhang angle.
  6. 6. The method for evaluating manufacturability of lattice structure based on processing paths according to claim 1 or 2, wherein in constraint three, the free length of the n+1th layer processing path satisfies: ; Wherein, the The furthest distance from the pattern obtained by performing the Boolean difference between the region formed by the path of the n+1th layer and the region formed by the path of the n layer to the region formed by the path of the n layer, Is a preset maximum allowable free length.
  7. 7. The method for evaluating manufacturability of lattice structure based on processing paths of claim 6, wherein the n+1th layer processing path satisfies: ; Wherein, the Representing a region The number of connected domains in the (c) pipeline, The shape of the n-th layer formed by the processing path is shown.
  8. 8. The method for evaluating manufacturability of lattice structure based on processing paths of claim 7, wherein the n-th layer has a shape formed by processing paths of The calculation formula of (2) is as follows: ; Wherein, the Is the first The level set function of the region outline formed by the tracks has the following calculation formula: ; Wherein, the , Representation of The Euler distance on the upper part of the frame, Is a path Upper distance The point of the closest approach is, Is the width of the melt channel.
  9. 9. The method for evaluating manufacturability of lattice structures based on processing paths according to claim 1, wherein: and integrating all the processing path grades, and taking the lowest grade as the grade corresponding to the lattice cell.
  10. 10. The method for evaluating manufacturability of a lattice structure based on a processing path according to claim 1, wherein the lattice unit cell is a three-period minimum curved surface structure.

Description

Lattice structure manufacturability evaluation method based on processing path Technical Field The invention relates to the technical field of additive manufacturing, in particular to a processing path-based lattice structure manufacturability evaluation method. Background The three-dimensional lattice structure/material has extremely low density, excellent mechanical property and excellent energy absorption capacity, and is a strategic new material meeting the requirements of light weight and multiple functions. The large-scale micro-lattice structure with the number of cells exceeding one hundred thousand or even millions and the characteristic size smaller than 100 mu m is widely existing in the nature and shows excellent physical properties and mechanical properties. The lattice structure/material has wide application in the fields of aerospace, biomedical, construction and the like due to the excellent mechanical and physical properties. While additive manufacturing (Additive Manufacturing, AM) technology provides a new approach to the fabrication of complex lattice structures, efficient design and accurate fabrication of lattice structures with a huge number of fine cells remains a current challenge. At present, the LPBF technology is limited by equipment, a data processing mode and a process mode, and is difficult to realize high-precision forming of a large-scale lattice structure with the feature size below 200 mu m. Meanwhile, for evaluation of manufacturability of lattice structures, existing means cannot be used for manufacturability analysis of such lattice cells generated based on processing paths. Disclosure of Invention The invention aims to provide an evaluation method of LPBF lattice structure manufacturability based on a processing path directly without depending on a geometric model, which can realize efficient and accurate manufacturability prediction and effectively solve the problems of difficult high-precision forming of a large-scale lattice structure, the lack of the lattice structure manufacturability evaluation method and the like. In order to solve the technical problems, the invention adopts the following technical scheme that the method for evaluating the manufacturability of the lattice structure based on the processing path generates a processing path model of the lattice element based on parameters of the lattice element, wherein the processing path model comprises a plurality of layers of processing paths, and performs the following operations on the plurality of layers of processing paths: sequentially carrying out constraint one, constraint two and/or constraint three on each processing path, and obtaining the grade of the corresponding processing path: Constraint one, wherein the wall thickness of the lattice unit cells is not smaller than the minimum value of the width of the processing path; constraint two, the processing path of the n+1th layer is contained in a constraint domain defined by the processing path of the n th layer; constraint III, the free length of the processing path is not more than the preset maximum allowed free length; And synthesizing manufacturability grades of the lattice unit cells by integrating all the processing path grades. Preferably, a hierarchical processing path evaluation mechanism is established to evaluate the grade of each layer of processing path, wherein the hierarchical processing path evaluation mechanism is as follows: If the constraint I is met, the grade of the processing path of the corresponding layer is 3, if the constraint II is met, otherwise, the grade of the processing path of the corresponding layer is 2, and if the constraint III is met, the grade of the processing path of the corresponding layer is 1; If constraint one is not satisfied, the grade of the processing path of the corresponding layer is 1. Preferably, in constraint one, a wall thickness t function of the array element cells is constructed,;In order to be the size of the cells,Relative area fraction/volume fraction of cellsIn the time-course of which the first and second contact surfaces,The minimum value of the machining path width is evaluated as meeting constraint one. Preferably, in constraint two, when the processing path of the n+1th layerContained in a constraint domain defined by an nth layer processing pathWhen, it is evaluated that constraint two is satisfied, namely: ; wherein the constraint domain From the formulaThe definition of the term "a" or "an" is,The processing path constraint area of the n+1th layer is obtained by taking boolean as m constraint areas defined by m processing paths of the n-th layer. Preferably, the processing path of the n+1th layerFalling at a distance from the nth layer of processing pathIn the region of (2), the expression is: ; Wherein, the As a function of the distance,Representing the processing path of the ith on the nth layer; Is the maximum distance between the center line of the n+1th layer molten pool and