CN-121990019-A - Safety host for computer blocking equipment and control method

CN121990019ACN 121990019 ACN121990019 ACN 121990019ACN-121990019-A

Abstract

The invention provides a safety host for computer blocking equipment and a control method thereof, which adopts a 2 by 2 redundant architecture comprising a driver break off A system, a driver break off B system, a safety motherboard A system, a safety motherboard B system and a switching board. The driver break off collects the original state of the external relay, the safety motherboard uses at least two processors to execute the blocking logic operation to obtain a plurality of results, the results are output to the corresponding driver break off in the main control state, the driver break off compares the results, and a driving signal is generated to control the relay when the results are consistent. The switching board is used for controlling the security motherboard A or the security motherboard B to be in a master control state. The scheme realizes the purposes of reducing the complexity of software and hardware, manufacturing cost and uninterrupted switching during faults and ensuring continuous operation of the blocking function.

Inventors

JI YINGJIE
ZHANG WEI
WANG XIAOHUI
TAO JING
LIU ZHONGJUN
ZHOU JIAN
LI XUJIANG
LIU YAGANG

Assignees

中国铁路成都局集团有限公司
通号(西安)轨道交通工业集团有限公司北京分公司

Dates

Publication Date: 20260508
Application Date: 20260203

Claims (10)

1. A safety host for computer blocking equipment is characterized by comprising a driver break off A system, a driver break off B system, a safety motherboard A system, a safety motherboard B system and a switching board; the driver break off A and the driver break off B are connected with an external relay and are used for collecting the original state of the external relay; The security motherboard a is connected to the driver break off a, and is configured to receive the original state, perform a blocking logic operation based on the original state by using at least two processors to obtain a plurality of operation results, and output the plurality of operation results obtained by the security motherboard a to the driver break off a when the security motherboard a is in a master state; The security motherboard B is connected to the driver break off B, and is configured to receive the original state, perform a blocking logic operation based on the original state by using at least two processors to obtain a plurality of operation results, and output the plurality of operation results obtained by the security motherboard B to the driver break off B when the security motherboard B is in a master state; The driver break off a is configured to take and compare a plurality of operation results obtained by the security motherboard a, and if the comparison is consistent, generate a first driving signal to drive the external relay; The driver break off B is configured to take and compare a plurality of operation results obtained by the security motherboard B, and if the comparison is consistent, generate a second driving signal to drive the external relay; The switching board is connected with the safety motherboard A system and the safety motherboard B system and used for controlling the safety motherboard A system or the safety motherboard B system to be in a master control state.
2. The security host of claim 1, wherein the security motherboard A comprises a first processor and a second processor; The first processor and the second processor are heterogeneous processors, respectively receive the original state, independently execute blocking logic operation based on the original state to obtain a first operation result and a second operation result, and output the first operation result and the second operation result to the drive break off A when the security motherboard A is in a master control state; correspondingly, the security motherboard B comprises a fourth processor and a fifth processor; The fourth processor and the fifth processor are heterogeneous processors, respectively receive the original state, independently execute the blocking logic operation based on the original state to obtain a third operation result and a fourth operation result, and output the third operation result and the fourth operation result to the driver break off B when the security motherboard B is in the master control state.
3. The security host of claim 2, wherein the security motherboard A further comprises a third processor, and the security motherboard B further comprises a sixth processor; The third processor is connected with the first processor and the second processor and is used for generating first own station blocking state information based on the first operation result and the second operation result and sending the first own station blocking state information to a neighboring station; The sixth processor is connected to the fourth processor and the fifth processor, and is configured to generate second own station blocking state information based on the third operation result and the fourth operation result, and send the second own station blocking state information to a neighboring station.
4. The security host of claim 3, wherein the security host further comprises a communication unit; The communication unit is connected with the third processor and the sixth processor, and is used for adopting an RSSP-1 security protocol to package and forwarding the information to an adjacent station through an optical fiber when the first local station blocking state information or the second local station blocking state information is obtained.
5. The safety-host of claim 3 wherein the third processor is connected to an all-electronic interlock system via ethernet for transmitting the first home-station occlusion status information to the all-electronic interlock system; The sixth processor is connected with the all-electronic interlocking system through an Ethernet and is used for sending the blocking state information of the second home station to the all-electronic interlocking system.
6. The security host of claim 2, wherein the driver break off A comprises a seventh processor, an eighth processor, a first comparator, and a plurality of first collection points; The seventh processor is connected with the first processor, the first comparator and a plurality of first acquisition points, and the plurality of first acquisition points are connected with an external relay; The seventh processor is configured to collect original states of the external relay by using a plurality of first collection points, and transmit the original states to the first processor; The eighth processor is connected with the second processor, the first comparator and a plurality of first acquisition points, and the plurality of first acquisition points are connected with an external relay; The eighth processor is configured to collect original states of the external relay by using a plurality of first collection points, and transmit the original states to the second processor; The first comparator is used for comparing the first operation result with the second operation result, and if the comparison is consistent, a first driving signal is generated to drive the external relay.
7. The security host of claim 2, wherein the driver break off B comprises a ninth processor, a tenth processor, a second comparator, and a plurality of second collection points; the ninth processor is connected with the fourth processor, the second comparator and a plurality of second acquisition points, and the second acquisition points are connected with an external relay; the ninth processor is configured to collect original states of the external relay by using a plurality of second collection points, and transmit the original states to the fourth processor; The tenth processor is connected with the fifth processor, the second comparator and a plurality of second acquisition points, and the second acquisition points are connected with an external relay; The tenth processor is configured to collect the original states of the external relay by using a plurality of second collection points, and transmit the original states to the fifth processor; and the second comparator is used for comparing the third operation result with the fourth operation result, and generating the second driving signal to drive the external relay if the comparison is consistent.
8. The safety master according to claim 2, wherein the driver break off A is further configured to send a periodic pulse sequence to the external relay and read back a first response signal of the external relay, and if the first response signal is inconsistent with the pulse sequence, stop outputting the first driving signal; the driver break off B is further configured to send a periodic pulse sequence to the external relay, and read back a second response signal of the external relay, and if the second response signal is inconsistent with the pulse sequence, stop outputting the second driving signal.
9. The security host of claim 1, wherein the switch board comprises a first health signal input unit, a second health signal input unit, a first status output unit, and a second status output unit; the first health signal input unit is connected with the safety motherboard A system and is used for receiving a first health state signal and a first heartbeat signal of the safety motherboard A system; The second health signal input unit is connected with the security motherboard B system and is used for receiving a second health state signal and a second heartbeat signal of the security motherboard B system; The first state output unit is connected with the first health signal input unit and the safety motherboard A system; The second state output unit is connected with the second health signal input unit and the safety motherboard B system; The first state output unit and the second state output unit are mutually connected to form a hardware interlock, and are used for determining that the safety motherboard A or the safety motherboard B is in a master control state according to the first health state signal, the first heartbeat signal, the second health state signal and the second heartbeat signal through hardware interlock logic and outputting a master control state signal to the safety motherboard determined as the master control state in the safety motherboard A or the safety motherboard B.
10. A control method, suitable for use with the security host of any one of claims 1 to 9, the method comprising: the driver break off A and the driver break off B collect the original states of the external relay; the switch board is used to control the security motherboard A or B to be in the master control state; The security motherboard A receives the original state, performs a blocking logic operation based on the original state by using at least two processors to obtain a plurality of operation results, and outputs the plurality of operation results obtained by the security motherboard A to the driver break off A when the security motherboard A is in a master control state; The security motherboard B receives the original state, performs a blocking logic operation based on the original state by using at least two processors to obtain a plurality of operation results, and outputs the plurality of operation results obtained by the security motherboard B to the driver break off B when the security motherboard B is in a master control state; The driver break off a is configured to compare the multiple operation results obtained by the security motherboard a, and generate a first driving signal to drive the external relay if the comparison results are consistent; the driver break off B performs a comparison between the multiple operation results obtained by the security motherboard B, and generates a second driving signal to drive the external relay if the comparison is consistent.

Description

Safety host for computer blocking equipment and control method Technical Field The invention relates to the technical field of rail transit safety, in particular to a safety host for computer blocking equipment and a control method. Background The blocking equipment is key equipment for ensuring the safety and the operation efficiency of railway transportation, at present, the single-line railway in China has about 4 ten thousand kilometers, the blocking mode adopts 64D type relay semi-automatic blocking, the system can be overlapped with a metering shaft to finish the upgrade of an automatic inter-station blocking system, and can also be combined with an inter-station safety information transmission system to finish the replacement of inter-station information from real loop to optical fiber transmission, but the blocking logic is still ensured by the relay circuit. At present, a digital blocking device based on a computer is an industry consensus, the computer blocking device takes a computer as a core, and logic control and safety interlocking of blocking and semi-automatic blocking sections between automatic stations are realized through combination of software and hardware, so that the running safety of a train in the sections is ensured, and the section passing capacity is improved. In the prior art, the universal interlocking platform is used for realizing redundancy of architecture when a scene is blocked, the cost is high, and the single-system safety architecture cannot realize uninterrupted switching when a fault occurs. Disclosure of Invention In view of this, the embodiment of the invention provides a safety host and a control method for implementing the blocking function, so as to achieve the purposes of reducing the complexity of software and hardware, manufacturing cost, and ensuring continuous operation of the blocking function by uninterrupted switching in the event of failure. In order to achieve the above object, the embodiment of the present invention provides the following technical solutions: The first aspect of the embodiment of the invention discloses a safety host for computer blocking equipment, which comprises a driver break off A system, a driver break off B system, a safety motherboard A system, a safety motherboard B system and a switching board; the driver break off A and the driver break off B are connected with an external relay and are used for collecting the original state of the external relay; The security motherboard a is connected to the driver break off a, and is configured to receive the original state, perform a blocking logic operation based on the original state by using at least two processors to obtain a plurality of operation results, and output the plurality of operation results obtained by the security motherboard a to the driver break off a when the security motherboard a is in a master state; The security motherboard B is connected to the driver break off B, and is configured to receive the original state, perform a blocking logic operation based on the original state by using at least two processors to obtain a plurality of operation results, and output the plurality of operation results obtained by the security motherboard B to the driver break off B when the security motherboard B is in a master state; The driver break off a is configured to take and compare a plurality of operation results obtained by the security motherboard a, and if the comparison is consistent, generate a first driving signal to drive the external relay; The driver break off B is configured to take and compare a plurality of operation results obtained by the security motherboard B, and if the comparison is consistent, generate a second driving signal to drive the external relay; The switching board is connected with the safety motherboard A system and the safety motherboard B system and used for controlling the safety motherboard A system or the safety motherboard B system to be in a master control state. Optionally, the security motherboard A comprises a first processor and a second processor; The first processor and the second processor are heterogeneous processors, respectively receive the original state, independently execute blocking logic operation based on the original state to obtain a first operation result and a second operation result, and output the first operation result and the second operation result to the drive break off A when the security motherboard A is in a master control state; correspondingly, the security motherboard B comprises a fourth processor and a fifth processor; The fourth processor and the fifth processor are heterogeneous processors, respectively receive the original state, independently execute the blocking logic operation based on the original state to obtain a third operation result and a fourth operation result, and output the third operation result and the fourth operation result to the driver break off B when the security motherboard B is in