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CN-121990521-A - CMUT (capacitive micro-electro-mechanical transducer) preparation method and CMUT

CN121990521ACN 121990521 ACN121990521 ACN 121990521ACN-121990521-A

Abstract

The invention belongs to the technical fields of micro-electromechanical systems and ultrasonic sensing, and discloses a CMUT and a preparation method thereof. The method of the invention uses the thickness of the first silicon oxide layer to define the cavity depth by establishing a double self-stopping high-precision control system, uses the doped layer as a stop surface during etching, eliminates the problem of uneven etching depth, and ensures the atomic-level uniformity of the thickness of the vibrating diaphragm by utilizing the doped layer in combination with wet etching selectivity. In addition, the method of the invention prepares the high-performance CMUT with uniform thickness and consistent depth by combining the doping self-stop technology and the double common monocrystalline silicon wafer bonding technology, thereby remarkably reducing the preparation cost. In addition, the method structurally solves the problem of insulation failure, adopts the idea that double wafers respectively define the structure and the function, places the second silicon dioxide layer forming the insulation layer on the flat second wafer, and thoroughly eliminates the breakdown risk of the insulation layer at the corner of the cavity caused by insufficient step coverage in the traditional process.

Inventors

  • ZHENG ZHOU
  • ZHENG HOUWEN
  • CAO JINLONG

Assignees

  • 芯旸微(苏州)电子有限公司

Dates

Publication Date
20260508
Application Date
20260202

Claims (10)

  1. 1. A method for preparing a CMUT, comprising the steps of: step 1, forming a doped layer with the same thickness as a vibrating diaphragm of a target CMUT device on the front surface of a first wafer; Step 2, growing silicon oxide layers on the front side and the back side of the first wafer at the same time; defining a cavity pattern, and removing the first silicon oxide layer of the cavity area until the doped layer is exposed; Step 3, selecting a second wafer with the same diameter as the first wafer, growing silicon oxide layers on the front surface and the back surface of the second wafer at the same time, and taking the silicon oxide layer on the front surface of the second wafer as a second silicon oxide layer; The first wafer and the second wafer are monocrystalline silicon wafers; the thickness of the second silicon dioxide layer is equal to the difference between the total thickness of the insulating layer and the depth of the cavity of the target CMUT device; Step 4, cleaning and activating the processed first wafer and second wafer, and performing fusion bonding on the front surface of the first wafer and the front surface of the second wafer in a vacuum environment; Step 5, firstly removing a silicon oxide layer on the back surface of the first wafer and part of silicon material of the first wafer by mechanical grinding, then corroding the rest silicon material of the first wafer by using wet etching liquid sensitive to doping concentration until the doping layer is exposed, and then performing surface polishing treatment to obtain a monocrystalline silicon diaphragm formed by the doping layer; and 6, manufacturing an electrode, and manufacturing the target CMUT device through wafer segmentation.
  2. 2. The CMUT manufacturing method of claim 1, wherein the step 1 specifically comprises: the surface of the first wafer is polished on one side or two sides; if the surface of the first wafer is polished on one side, the polished surface is the front surface of the first wafer, and the unpolished surface is the back surface of the first wafer; Through the pretreatment of the first wafer, a doped layer is formed on the front surface of the first wafer, the thickness of the doped layer is equal to the thickness of the vibrating diaphragm of the target CMUT device, and the doped layer is formed by adopting any one of ion implantation, thermal diffusion and epitaxial growth.
  3. 3. The CMUT manufacturing method of claim 1, wherein the step 2 specifically comprises: Simultaneously growing silicon oxide layers on the front side and the back side of the first wafer through a thermal oxidation process, taking the silicon oxide layer positioned on the front side of the first wafer as a first silicon oxide layer, wherein the thickness of the first silicon oxide layer is equal to the depth of a cavity of the target CMUT device; and defining the pattern of the cavity area by using a photoetching process, and removing the first silicon oxide layer of the cavity area by using a dry etching or wet etching process until the doped layer below the first silicon oxide layer is exposed and automatically stops.
  4. 4. The CMUT manufacturing method of claim 1, wherein the step 3 specifically comprises: the surface of the second wafer is polished on one side or two sides; If the surface of the second wafer is polished on one side, the polished surface is the front surface of the second wafer, and the unpolished surface is the back surface of the second wafer; and simultaneously growing a silicon oxide layer on the front surface and the back surface of the second wafer through a thermal oxidation process, taking the silicon oxide layer positioned on the front surface of the second wafer as a second silicon oxide layer, wherein the thickness of the second silicon oxide layer is equal to the difference value between the total thickness of the insulating layer and the depth of the cavity of the target CMUT device, and keeping the second silicon oxide layer in a plane growth state without any etching.
  5. 5. The CMUT manufacturing method of claim 1, wherein the step 5 specifically comprises: Removing the silicon oxide layer and part of the silicon substrate on the back surface of the first wafer in a mechanical grinding mode, wherein the removed part of the silicon substrate is part of the bulk silicon material on the back surface of the first wafer, so that the bulk silicon material of the first wafer keeps the allowance of 10-50 microns away from the doped layer; etching the residual bulk silicon material of the first wafer by adopting a wet etching solution sensitive to doping concentration, wherein the etching process is stopped on the surface of the doping layer, and the wet etching solution is any one of KOH, TMAH, EDP solutions; and then carrying out CMP polishing to remove the surface roughness, thereby obtaining the monocrystalline silicon diaphragm which is high in uniformity of thickness and consists of the doped layer.
  6. 6. The CMUT manufacturing method of claim 1, wherein the step 6 specifically comprises: firstly, defining a scribing channel region between a lower electrode contact hole pattern and a bare DIE, and removing doped layers of the electrode contact hole and the scribing channel region by adopting a dry etching process until a first silicon oxide layer is exposed; Defining a scribing channel region between the lower electrode contact hole pattern and the bare DIE again, and removing the first silicon oxide layer and the second silicon oxide layer of the electrode contact hole and the scribing channel region by adopting a dry etching process or a wet etching process until the silicon substrate of the second wafer at the bottom is completely exposed; Preparing a metal interconnection layer by adopting a stripping process; And cutting along the scribing channel to obtain the target CMUT device.
  7. 7. The method of manufacturing a CMUT according to claim 6, wherein in step 6, the dry etching process employs reactive ion etching RIE or deep reactive ion etching DRIE.
  8. 8. The CMUT manufacturing method according to claim 6, wherein in the step 6, the process of manufacturing the metal interconnection layer by using the lift-off process specifically comprises: Defining patterns of the electrode and the bonding pad by using a photoetching process, and reserving photoresist in a preset nonmetallic area; then depositing a conductive metal layer by utilizing an electron beam evaporation or magnetron sputtering process; And then removing the photoresist of the non-metal area and the conductive metal layer attached to the photoresist, so that an upper electrode and an upper electrode pad are formed on the surface of the vibrating diaphragm at the same time, and a lower electrode pad which is conducted with the silicon substrate of the second wafer is formed at the contact hole of the lower electrode.
  9. 9. The method for preparing the CMUT according to claim 6, wherein in the step 6, the process of cutting along the scribe line to obtain the target CMUT device is specifically: Attaching a blue film on the back surface of the second wafer after the preparation of the metal interconnection layer, and physically cutting along a scribing channel by using an automatic scribing machine to divide the whole wafer into a plurality of independent bare DIEs; and finally, obtaining the target CMUT device, namely a single CMUT chip, through a grain picking process.
  10. 10. A CMUT prepared by the CMUT preparation method of any one of claims 1 to 9.

Description

CMUT (capacitive micro-electro-mechanical transducer) preparation method and CMUT Technical Field The invention belongs to the technical field of micro-electromechanical systems and ultrasonic sensing, and particularly relates to a CMUT (capacitive micro-electromechanical system) preparation method and a CMUT. Background The capacitive micromachined ultrasonic transducer CMUT is a new generation ultrasonic transducer based on MEMS technology, has the advantages of small size, wide frequency band, high sensitivity, high compatibility with CMOS circuits and the like, and has become an important development direction in the fields of medical ultrasonic imaging, industrial detection and the like. The core structure of the device consists of a substrate, an insulating layer, a vacuum cavity, a vibrating diaphragm and an electrode. The current main CMUT manufacturing process mainly comprises a sacrificial layer release method and a wafer bonding method. The sacrificial layer release method is early in application, but the process flow is complex, and in the process of removing the sacrificial layer, the phenomenon that the diaphragm is adhered to the substrate is very easy to occur, and the yield and the performance consistency of the device are seriously affected, so that the preparation technology based on wafer bonding gradually becomes the preferred scheme for manufacturing the high-performance CMUT. In the existing wafer bonding process, the industry generally adopts a silicon-on-insulator (SOI) wafer to bond with a silicon oxide substrate with a cavity, and then removes a substrate layer and a buried oxide layer of the SOI to obtain the required monocrystalline silicon diaphragm. Although this process can achieve better diaphragm thickness control, the expensive SOI wafer greatly increases the production cost of CMUT, limiting its wide application in the large-scale consumer electronics field. To find low cost alternatives, some studies have attempted to construct CMUT diaphragms with materials such as silicon dioxide or photoresist polymers such as SU-8. However, silicon dioxide diaphragms often have huge residual stress in the preparation process, which is easy to cause the diaphragm to warp, and polymer materials such as SU-8 have Young's modulus far lower than that of monocrystalline silicon, which causes insufficient rigidity of the diaphragm and is easy to generate acoustic loss, and the diaphragm has poor performance in high-frequency response, energy conversion efficiency and environmental stability. In addition, the construction of CMUT cavities on silicon oxide substrates also faces a number of technical challenges. On the one hand, if the cavity depth is defined by adopting reactive ion etching, the etching rate is obviously influenced by equipment state and process drift, so that the cavity depth is uneven, and further the resonant frequency of the vibrating diaphragm and the consistency of devices are influenced. On the other hand, if the silicon substrate is etched until reaching the depth of the cavity to form the cavity, and then the thermal oxide layer is regrown to serve as an insulating layer, although the problem of cavity depth control is solved, the problem of uneven thickness, stress concentration and the like of the secondarily grown oxide layer can be generated at the edge of the cavity, particularly at the corner, and the yield and the device pressure resistance are reduced. Therefore, the existing CMUT manufacturing process has obvious disadvantages in terms of cost, cavity depth uniformity and insulating layer quality, and a new manufacturing method is needed to solve the above problems. Disclosure of Invention The invention aims to provide a CMUT preparation method, which can solve the technical bottlenecks that the cavity depth is difficult to accurately control in the traditional bulk silicon process and the pressure resistance is poor due to the corner effect of an insulating layer while greatly reducing the production cost through double common monocrystalline silicon wafer bonding and doping self-stopping thinning processes. In order to achieve the above purpose, the invention adopts the following technical scheme: A CMUT manufacturing method comprising the steps of: step 1, forming a doped layer with the same thickness as a vibrating diaphragm of a target CMUT device on the front surface of a first wafer; Step 2, growing silicon oxide layers on the front side and the back side of the first wafer at the same time; defining a cavity pattern, and removing the first silicon oxide layer of the cavity area until the doped layer is exposed; Step 3, selecting a second wafer with the same diameter as the first wafer, growing silicon oxide layers on the front surface and the back surface of the second wafer at the same time, and taking the silicon oxide layer on the front surface of the second wafer as a second silicon oxide layer; The first wafer and the second wafer are monocrysta