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CN-121995103-A - Voltage spike detection

CN121995103ACN 121995103 ACN121995103 ACN 121995103ACN-121995103-A

Abstract

The present disclosure relates to a power supply voltage glitch detection circuit (300) comprising a first flip-flop (301) having a data input (302), a clock input (303) and an output (304), a delay circuit (305) having an output (307) connected to the data input of the first flip-flop, a first clock signal divider (308) having a clock input (309) connected to receive an inverted clock signal and an output (312) connected to an input (306) of the delay circuit (305), a second clock signal divider (313) having a clock input (314) connected to receive the clock signal and an output (315) connected to the clock input (303) of the first flip-flop, wherein the circuit (300) is configured to cause a glitch detection signal output to change state upon a power supply voltage of the circuit (300) deviating to cause a change in delay provided by the delay circuit (305).

Inventors

  • LI XIANCHENG

Assignees

  • 恩智浦有限公司

Dates

Publication Date
20260508
Application Date
20251107
Priority Date
20241108

Claims (10)

  1. 1. A supply voltage glitch detection circuit (300, 400, 500), characterized in that it comprises: A first flip-flop (301) having a data input (302), a clock input (303) and an output (304) for providing a glitch detection signal (OUT); -a delay circuit (305) having an input (306) and an output (307) connected to the data input (302) of the first flip-flop (301); A first clock signal divider (308) having a clock input (309) connected to receive an inverted clock signal and an output (312) connected to the input (306) of the delay circuit (305); A second clock signal divider (313) having a clock input (314) connected to receive the clock signal (CLK) and an output (315) connected to the clock input (303) of the first flip-flop (301), Wherein the supply voltage glitch detection circuitry (300, 400, 500) is configured to cause the glitch detection signal (OUT) to change state upon a supply voltage of the circuitry (300, 400, 500) deviating to cause a change in delay provided by the delay circuitry (305).
  2. 2. The supply voltage glitch detection circuit (300, 400, 500) of claim 1, in which: The first clock signal divider includes a second flip-flop (308) having a data input (317) and an inverted output (318), the data input (317) being connected to the inverted output (318), and The second clock signal divider includes a third flip-flop (313) having a data input (319) and an inverted output (320), the data input (319) being connected to the inverted output (320).
  3. 3. The supply voltage glitch detection circuit (300) of claim 1 or claim 2, in which said supply voltage glitch detection circuit comprises an inverter (311) connected between said clock input (309) of said first clock signal divider (308) and a clock signal line (310), in which said clock input (314) of said second clock signal divider (313) is connected to said clock signal line (310).
  4. 4. A supply voltage glitch detection circuit according to any of claims 1 to 3, in which the output (312) of the first clock signal divider (308) is directly connected to the input (306) of the delay circuit (305).
  5. 5. A supply voltage glitch detection circuit (400, 500) according to claim 2 or claim 3, in which the supply voltage glitch detection circuit further comprises a logic and gate (401) having a first input connected to the output (312) of the second flip-flop (308), a second input connected to the inverted output (320) and data input (319) of the third flip-flop (313), and an output connected to the input (306) of the delay circuit (305).
  6. 6. The supply voltage spur detector circuit (500) according to claim 1, wherein the clock signal is a divided clock signal, the detector circuit (500) further comprising: A third clock signal divider (501) having a clock input (503) connected to receive an inverted clock signal and an output (504) connected to the clock input (309) of the first clock signal divider (308) for providing an inverted divided clock signal to the first clock signal divider (308), and A fourth clock signal divider (502) having a clock input (505) connected to receive the clock signal and the clock input (309) connected to the second clock signal divider (313) for providing the divided clock signal to an output (506) of the second clock signal divider (313).
  7. 7. The supply voltage spur detector circuit (500) according to claim 6, wherein: The third clock divider comprises a fourth flip-flop (501) having a data input (507) and an inverted output (508), the data input (507) being connected to the inverted output (508), and The fourth clock signal divider comprises a fifth flip-flop (502) having a data input (509) and an inverted output (510), the data input (509) being connected to the inverted output (510).
  8. 8. The supply voltage glitch detection circuit (500) of claim 6 or claim 7, in which said supply voltage glitch detection circuit comprises an inverter (311) connected between said clock input (503) of said third clock signal divider (501) and a clock signal line (310), in which said clock input (505) of said fourth clock signal divider (502) is connected to said clock signal line (310).
  9. 9. The supply voltage glitch detection circuit of any of claims 6 to 8, in which said output (312) of said first clock signal divider (308) is directly connected to said input (306) of said delay circuit (305).
  10. 10. A method of detecting a supply voltage spur using a detector circuit (300, 400, 500), the detector circuit comprising: A first flip-flop (301) having a data input (302), a clock input (303) and an output (304) for providing a glitch detection signal (OUT); -a delay circuit (305) having an input (306) and an output (307) connected to the data input (302) of the first flip-flop (301); A first clock signal divider (308) having a clock input (309) connected to receive an inverted clock signal and an output (312) connected to the input (306) of the delay circuit (305); A second clock signal divider (313) having a clock input (314) connected to receive the clock signal and an output (315) connected to the clock input (303) of the first flip-flop (301), Wherein the delay circuit (305) provides a delay of at least one half of a clock period of a clock signal with a supply voltage of the circuit at a nominal level, and the glitch detection signal (OUT) changes state when an increase in the supply voltage causes the delay to drop below one half of the clock period.

Description

Voltage spike detection Technical Field The present disclosure relates to circuits and methods for detecting voltage glitches. Background Voltage glitches, i.e., temporary increases or decreases in the supply voltage, in digital circuits can be used to extract information from otherwise secure circuits. The intentional introduction of voltage glitches may introduce faults into the circuit, which may be used to cause the circuit to output sensitive information, such as an internally stored encryption or decryption key. Thus, detecting and/or mitigating the effects of such attacks is an important feature in designing more resilient security circuits. Disclosure of Invention According to a first aspect, there is provided a power supply voltage glitch detection circuit comprising a first flip-flop having a data input, a clock input and an output for providing a glitch detection signal, a delay circuit having an input and an output connected to the data input of the first flip-flop, a first clock signal divider having an output connected to receive the clock input of the inverted clock signal and to the input of the delay circuit, and a second clock signal divider having a clock input connected to receive the clock signal and an output connected to the clock input of the first flip-flop, wherein the voltage glitch detection circuit is configured to cause the glitch detection signal to change state upon a power supply voltage of the circuit being deviated to cause a change in delay provided by the delay circuit. In some examples, the first clock signal divider includes a second flip-flop having a data input and an inverted output, the data input being connected to the inverted output, and the second clock signal divider includes a third flip-flop having a data input and an inverted output, the data input being connected to the inverted output. In some examples, the supply voltage glitch detection circuitry includes an inverter connected between a clock input of the first clock signal divider and the clock signal line, wherein a clock input of the second clock signal divider is connected to the clock signal line. In an alternative example, the supply voltage glitch detection circuitry includes an inverter connected between a clock input of the second clock signal divider and the clock signal line, wherein the clock input of the first clock signal divider is connected to the clock signal line. In some examples, the output of the first clock signal divider is directly connected to the input of the delay circuit. In some examples, the supply voltage glitch detection circuitry further comprises a logic and gate having a first input connected to the output of the second flip-flop, a second input connected to the inverted output and the data input of the third flip-flop, and an output connected to the input of the delay circuit. In some examples, the clock signal is a divided clock signal, the detector circuit further includes a third clock signal divider having a clock input connected to receive the inverted clock signal and a clock input connected to the first clock signal divider for providing the inverted divided clock signal to an output of the first clock signal divider, and a fourth clock signal divider having a clock input connected to receive the clock signal and a clock input connected to the second clock signal divider for providing the divided clock signal to an output of the second clock signal divider. In some examples, the third clock signal divider includes a fourth flip-flop having a data input and an inverted output, the data input being connected to the inverted output, and the fourth clock signal divider includes a fifth flip-flop having a data input and an inverted output, the data input being connected to the inverted output. In some examples, the supply voltage glitch detection circuitry includes an inverter connected between a clock input of the third clock signal divider and the clock signal line, wherein the clock input of the fourth clock signal divider is connected to the clock signal line. In some alternative examples, the supply voltage glitch detection circuitry includes an inverter connected between a clock input of the fourth clock signal divider and the clock signal line, wherein the clock input of the third clock signal divider is connected to the clock signal line. The output of the first clock signal divider may be directly connected to the input of the delay circuit. Alternatively, the supply voltage glitch detection circuitry further comprises a logic and gate having a first input connected to the output of the second flip-flop, a second input connected to the inverted output and the data input of the third flip-flop, and an output connected to the input of the delay circuit. According to a second aspect there is provided a method of detecting a glitch in a supply voltage using a detector circuit comprising a first flip-flop having a data input, a clock input and an output for prov