CN-121995131-A - Multichannel signal and power analyzer

Abstract

The present disclosure relates to multichannel signal and power analyzers. A signal and power analysis instrument includes one or more high bandwidth input channels configured as one or more real-time equivalent (RET) input channels and/or one or more Radio Frequency (RF) channels, one or more input channels configured as one or more low bandwidth real-time (RT) input channels, one or more analog-to-digital converters (ADCs) having pipes, a first set of pipes connected to the one or more high bandwidth input channels to generate high bandwidth data, and a second set of pipes connected to the one or more low bandwidth RT input channels to generate low bandwidth RT data, a system clock connected to the high bandwidth input channels and the low bandwidth RT input channels, a memory connected to the system clock, the first set of pipes and the second set of pipes, and one or more processors storing and aligning the low bandwidth RT data and the high bandwidth data in the memory.

Inventors

• TAN KAN

Assignees

• 特克特朗尼克公司

Dates

Publication Date

20260508

Application Date

20251107

Priority Date

20251103

Claims (20)

1. 1. A signal and power analysis instrument, comprising: One or more high bandwidth input channels configured to connect to at least one of one or more real-time equivalent time (RET) input channels or one or more Radio Frequency (RF) channels of a device under test DUT; one or more input channels configured as one or more low bandwidth Real Time (RT) input channels; One or more analog-to-digital converters (ADCs), each ADC having one or more pipes, a first set of one or more pipes connected to one or more high bandwidth input channels to produce high bandwidth data, and a second set of one or more pipes connected to one or more low bandwidth RT input channels to produce low bandwidth data; A system clock coupled to the one or more high bandwidth input channels and the one or more low bandwidth RT input channels; A memory coupled to the system clock, a first set of one or more pipes coupled to the one or more high bandwidth input channels, and a second set of one or more pipes coupled to the one or more low bandwidth RT input channels, and One or more processors configured to execute code that causes the one or more processors to: storing low bandwidth data from the second set of pipes in memory; Storing high bandwidth data from the first set of pipes in a memory, and The high bandwidth data and the low bandwidth data are aligned in time using a system clock.
2. 2. The signal and power analysis instrument of claim 1, wherein the one or more high bandwidth input channels comprise one or more RET input channels and one or more RF input channels, RET-only input channels, or RF-only input channels.
3. 3. The signal and power analysis instrument of claim 1, wherein the one or more high bandwidth input channels further comprise one or more high bandwidth RT input signal channels, and the instrument further comprises a third set of pipes connected to the one or more high bandwidth RT input signal channels.
4. 4. A signal and power analysis instrument according to claim 3, wherein the one or more high bandwidth input channels comprise one or more RET input channels and one or more high bandwidth RT input channels, one or more RF input channels and one or more high bandwidth RT channels, or one or more RET input channels, one or more RF input channels and one or more high bandwidth RT input channels.
5. 5. The signal and power analysis instrument of claim 3, wherein the one or more high bandwidth input channels comprise one or more RET input channels and the first set of pipes comprises fewer pipes than the number of pipes in the third set of pipes.
6. 6. The signal and power analysis instrument of claim 1, wherein the one or more high bandwidth input channels are configured to receive one or more signals from the DUT, and the high bandwidth data comprises signal data.
7. 7. The signal and power analysis instrument of claim 6, wherein the one or more low bandwidth RT input channels are configured to connect to a power source that powers the DUT, and the low bandwidth data comprises power data.
8. 8. The signal and power analysis instrument of claim 7, wherein the code that causes the one or more processors to time align high bandwidth data and low bandwidth data comprises code that aligns power data and signal data using a system clock.
9. 9. The signal and power analysis instrument of claim 6, wherein the signal data includes at least one of RET data and RF data.
10. 10. The signal and power analysis instrument of claim 6, wherein the signal data includes at least one of RET, RF, and high bandwidth RT data.
11. 11. A method of performing signal integrity and power integrity analysis, comprising: Receive one or more signals from one or more input channels configured as one or more low bandwidth Real Time (RT) input channels; Receiving one or more signals from a Device Under Test (DUT) from one or more high bandwidth input channels configured as one or more of a real-time equivalent time (RET) input channel and a Radio Frequency (RF) input channel; Generating low bandwidth RT data using a first set of one or more analog-to-digital converter pipelines (ADCs) connected to one or more low bandwidth RT input channels; Generating high bandwidth data using a second set of one or more ADC pipes connected to one or more high bandwidth input channels; Storing the high bandwidth data and the low bandwidth RT data in an acquisition memory, and The low bandwidth RT data and the high bandwidth data are aligned in time using a system clock.
12. 12. The method of claim 11, wherein receiving signals from one or more high bandwidth input channels comprises one or more of receiving signals from one or more RET input channels and one or more RF input channels, receiving signals from only one or more RET input channels, or receiving signals from only one or more RF input channels.
13. 13. The method of claim 11, further comprising receiving one or more signals from one or more high bandwidth RT input channels and using a third set of ADC pipes connected to the one or more high bandwidth RT input channels.
14. 14. The method of claim 13, wherein receiving one or more signals from one or more high bandwidth input channels can include receiving one or more of one or more signals from one or more RET input channels and one or more high bandwidth RT input channels, one or more RF input channels and one or more high bandwidth RT channels, or one or more RET input channels, one or more RF input channels and one or more high bandwidth RT input channels.
15. 15. The method of claim 13, wherein the one or more high bandwidth input channels comprise one or more RET input channels and the first set of pipes comprises fewer pipes than the number of pipes in the third set of pipes.
16. 16. The method of claim 13, wherein receiving the one or more signals from the DUT comprises receiving one or more signals of at least one of RET, RF, and high bandwidth RT signals.
17. 17. The method of claim 11, wherein receiving one or more signals from a DUT from one or more high bandwidth input channels comprises receiving signal data.
18. 18. The method of claim 17, wherein receiving one or more signals from the one or more low bandwidth RT input channels comprises receiving one or more signals from a power supply that powers the DUT, and receiving one or more signals from the one or more low bandwidth RT channels comprises receiving power data.
19. 19. The method of claim 18, wherein temporally aligning low bandwidth RT data and high bandwidth data comprises aligning power data and signal data.
20. 20. The method of claim 19, further comprising performing signal integrity and power integrity analysis on the time-aligned power data and signal data.

Description

Multichannel signal and power analyzer Cross Reference to Related Applications The present disclosure is a non-provisional application No. 63/718,480, U.S. provisional application No. 63/718,480, entitled "multichannel signal and POWER ANALYZER" (MULTI-CHANNEL SIGNAL AND POWER ANALYZER), filed on 8, 11, 2024, the disclosure of which is incorporated herein by reference in its entirety, and claims the benefit of this provisional application. Technical Field The present disclosure relates to test and measurement instruments, and more particularly, to a multi-channel combined signal and power analysis instrument. Background With the development of generative artificial intelligence, data centers, electric Vehicles (EV), 5G/6G wireless, quantum computing, there is an increasing demand for instruments with high channel counts and capable of performing combined Signal Integrity (SI) and Power Integrity (PI) analysis. High-speed wired data transmission enables the generation of artificial intelligence and data centers to cope with the ever-increasing data demands, requiring higher power to support data transmission and data processing. Industry standards such as IEEE ethernet 800G require high analog bandwidth oscilloscopes to measure their signal integrity. The power supply requires an oscilloscope with a much lower analog bandwidth to measure power integrity. Because of the correlation between Signal Integrity (SI) and Power Integrity (PI), an instrument that captures time-dependent signals for SI/PI analysis would allow users to learn more about their design. There is an unmet need for electric vehicles, 5G/6G wireless and quantum computing, requiring an instrument to capture and analyze time-dependent time domain signals, RF signals and power signals. The need for such an instrument comes from several aspects. Advances in generated artificial intelligence have led to significant developments in high performance computing infrastructure, including GPU clusters for LLM training and large data centers providing data storage, processing, and transmission. These applications require higher power. The adoption of global electric vehicles has increased the need for power analysis instrumentation. Modern vehicles are equipped with high-speed wired and wireless data communication systems to transmit video, radar and other sensor data. An increasing number of qubits are built into quantum computing systems, hundreds of which require spectrum analyzers with high channel counts. 5G and 6G wireless tests require spectrum analyzers with higher channel counts because they employ a massive multiple-input multiple-output (MIMO) architecture. For high-speed time-domain signals such as 800G PAM4 ethernet signals and high-bandwidth RF signals such as 5G and 6G wireless signals, signal Integrity (SI) analysis is required. Power supplies and motors require Power Integrity (PI) analysis. The interaction between the power supply and the signal path requires SI/PI analysis. SI/PI analysis was initially performed during the system design phase by simulation. When an actual system is produced, test instruments are used to verify the design and debug system. U.S. patent No. 11,789,051, issued on 10/17 at 2023, entitled "Real-time equivalent-time oscilloscope," describes a new class of oscilloscopes, namely Real-time equivalent-time (RET) oscilloscopes, the contents of which are incorporated herein by reference in their entirety. RET oscilloscopes use only a single ADC, and the sampling rate per channel is lower, thus greatly reducing complexity and cost compared to traditional real-time oscilloscopes, which typically have multiple interleaved ADCs to achieve a higher sampling rate. U.S. patent application publication No. 2024/0313795, filed on 2/29 of 2024, entitled "Real-time Equivalent oscilloscope and broadband Real-time spectrum analyzer (Real-time-Time oscilloscope and Wideband Real-Time Spectrum Analyzer)" describes a new class of instruments, the contents of which are incorporated by reference in their entirety into the present disclosure, which utilizes the RET oscilloscope architecture described in U.S. patent No. 11,789,051, so that the instruments can also operate as Real-time spectrum analyzers. Embodiments of the present disclosure utilize the techniques described in U.S. patent No. 11,789,051 and U.S. patent application publication No. 2024/0313795. Drawings Fig. 1 shows an embodiment of a signal and power analysis instrument. Fig. 2 shows a block diagram of an embodiment of signal and power analysis. Fig. 3 shows a block diagram of an embodiment of a channel architecture of a signal and power analysis instrument. Fig. 4 shows an example of a spectrogram of a signal resulting from a power integrity problem. Detailed Description Embodiments herein relate to a new instrument, referred to herein as a Signal and Power Analyzer (SPA). Generally, an SPA will have more channel counts whose system clock allows for synchronization si