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CN-121995190-A - Method for determining power consumption of chip

CN121995190ACN 121995190 ACN121995190 ACN 121995190ACN-121995190-A

Abstract

The application relates to the technical field of chip testing, in particular to a method for determining power consumption of a chip. The chip comprises n first-class clocks and m second-class clocks, the frequencies of the first-class clocks under different working scenes are the same or different, the frequencies of the second-class clocks under different working scenes are the same, n is more than or equal to 2, and m is more than or equal to 1. The application can accurately estimate the power consumption of the chip when the voltage V 0 and the frequency of the first type clock change.

Inventors

  • LI WENWEN
  • LIU YANGBO
  • ZHAO QIN

Assignees

  • 沐曦集成电路(上海)股份有限公司

Dates

Publication Date
20260508
Application Date
20241031

Claims (7)

  1. 1. A method for determining power consumption of a chip is characterized in that the chip comprises n first-class clocks and m second-class clocks, the frequencies of the first-class clocks under different working scenes are the same or different, the frequencies of the second-class clocks under different working scenes are the same, n is more than or equal to 2, m is more than or equal to 1, and the method comprises the following steps: S100, acquiring total current I t,1 of a chip in a first working scene, wherein the working voltage of the chip in the first working scene is V 0 , the frequency of a j first clock j of the chip in the first working scene is F j,1 , and the value range of j is 1 to n; S200, acquiring intercept current Ib j of clock j under the j-th condition, wherein the j-th condition comprises that the working voltage of a chip is V 0 , the frequency of an e-th first clock e of the chip is F e,1 , the value range of e is 1 to n, and e is not equal to j; S300, obtaining a first partial current I other ,I other ＝(∑ n j＝1 Ib j )-(n-1)×I t,1 of the chip when the working voltage is V 0 ; S400, acquiring total current I t,0 ,I t,0 ＝(∑ n j＝1 Cac j ×V 0 ×f j )+I other of a chip in a target working scene, wherein the working voltage of the chip in the target working scene is V 0 , and the frequency f j ,Cac j of clock j in the chip in the target working scene is the dynamic overturning capacitance of clock j when the working voltage of the chip is V 0 ; s500, determining V 0 ×I t,0 as the power consumption of the chip in the target working scene.
  2. 2. The method for determining power consumption of a chip according to claim 1, wherein the obtaining process of Ib j includes: S210, acquiring total current I t,2 of the chip in a second working scene, wherein the working voltage of the chip in the second working scene is V 0 , the frequency of clock e in the second working scene is F e,1 , and the frequency of clock j in the second working scene is F j,2 ,F j,1 ≠F j,2 ; s220, establishing a target coordinate system by taking the frequency of a clock j as a horizontal axis and the total current of a chip as a vertical axis; S230, drawing a j-th straight line in the target coordinate system according to a first point (F j,1 ,I t,1 ) and a second point (F j,2 ,I t,2 ) in the target coordinate system, wherein the j-th straight line passes through the first point (F j,1 ,I t,1 ) and the second point (F j,2 ,I t,2 ); and S240, determining a vertical axis coordinate corresponding to an intersection point of the jth straight line and the vertical axis as Ib j .
  3. 3. The method for determining power consumption of a chip according to claim 1, wherein the acquiring process of the Cac j includes: S410, acquiring total current I t,2 of the chip in a second working scene, wherein the working voltage of the chip in the second working scene is V 0 , the frequency of clock e in the second working scene is F e,1 , and the frequency of clock j in the second working scene is F j,2 ,F j,1 ≠F j,2 ; s420, establishing a target coordinate system by taking the frequency of a clock j as a horizontal axis and the total current of a chip as a vertical axis; S430, drawing a j-th straight line in the target coordinate system according to a first point (F j,1 ,I t,1 ) and a second point (F j,2 ,I t,2 ) in the target coordinate system, wherein the j-th straight line passes through the first point (F j,1 ,I t,1 ) and the second point (F j,2 ,I t,2 ); S440, acquiring the slope k j of the j-th line; S450, determining k j /V 0 as Cac j .
  4. 4. The method of claim 1, wherein the Cac e is a dynamic flip capacitor, ib j ＝(∑ n e＝1,e≠j Cac e ×V 0 ×F e,1 )+I other , of the clock e when the operating voltage of the chip is V 0 .
  5. 5. A method of determining power consumption of a chip according to claim 3, wherein k j ＝Cac j ×V 0 .
  6. 6. The method of determining power consumption of a chip according to claim 1, wherein the chip includes a number of clocks q, q=n+m.
  7. 7. The method of claim 1, wherein I other comprises a quiescent current of the chip at a voltage of V 0 and a dynamic current of m clocks of the second type.

Description

Method for determining power consumption of chip Technical Field The invention relates to the technical field of chip testing, in particular to a method for determining power consumption of a chip. Background The power consumption of the chip comprises static power consumption and dynamic power consumption, the power consumption of the chip under different voltages and frequencies is different, and the workload of acquiring the power consumption of the chip under each voltage and frequency by using a platform (system-level platform) is too large. In the prior art, the method for determining the power consumption generally aims at the situation that a chip corresponds to 1 clock (clock) with frequency needing to be changed in one power domain, but how to accurately estimate the power consumption of the chip under each voltage and frequency is a problem to be solved in the situation that the chip corresponds to 2 or more clocks with frequency needing to be changed in one power domain. Disclosure of Invention The invention aims to provide a method for determining the power consumption of a chip so as to accurately estimate the power consumption of the chip under various voltages and frequencies. According to the invention, a method for determining the power consumption of a chip is provided, wherein the chip comprises n first-class clocks and m second-class clocks, the frequencies of the first-class clocks under different working scenes are the same or different, the frequencies of the second-class clocks under different working scenes are the same, n is more than or equal to 2, m is more than or equal to 1, and the method comprises the following steps: s100, acquiring total current I t,1 of the chip in a first working scene, wherein the working voltage of the chip in the first working scene is V 0, the frequency of a j first clock j of the chip in the first working scene is F j,1, and the value range of j is 1 to n. S200, acquiring intercept current Ib j of clock j under the j-th condition, wherein the j-th condition comprises that the working voltage of a chip is V 0, the frequency of the e-th first clock e of the chip is F e,1, the value range of e is 1 to n, and e is not equal to j. S300, obtaining a first partial current I other,Iother＝(∑nj＝1Ibj)-(n-1)×It,1 of the chip when the working voltage is V 0. S400, acquiring total current I t,0,It,0＝(∑nj＝1Cacj×V0×fj)+Iother of the chip in a target working scene, wherein the working voltage of the chip in the target working scene is V 0, and the frequency f j,Cacj of clock j in the chip in the target working scene is the dynamic overturning capacitance of clock j when the working voltage of the chip is V 0. S500, determining V 0×It,0 as the power consumption of the chip in the target working scene. Compared with the prior art, the invention has at least the following beneficial effects: The invention can accurately estimate the power consumption of the chip under each voltage and frequency under the condition that one power domain of the chip corresponds to 2 or more clocks (namely first type clocks) needing to change frequency, for example, when the power consumption of the chip is to be estimated under the voltage V 0 and the frequency of the j first type clock j of the chip is f j, the total current I t,0,It,0＝(∑nj＝1Cacj×V0×fj)+Iother of the chip under the voltage V 0 and the frequency of the j first type clock j of the chip is f j is obtained, the invention can obtain I other by utilizing the formula I other＝(∑nj＝1Ibj)-(n-1)×It,1, I t,1 in the formula I other＝(∑nj＝1Ibj)-(n-1)×It,1 can be directly measured when the chip works under the first working scene, ib j can be obtained by fixing the frequency of other first type clocks except for the clock e of the chip as the frequency of the corresponding clock in the first working scene and changing the frequency of the clock j, n is also a known value, and the current can be accurately estimated under the voltage V 0 and the frequency of the first type clock according to the formula I other＝(∑nj＝1Ibj)-(n-1)×It,1 of the invention, and the current can be accurately estimated under the voltage V 0 when the frequency of the chip is the first type clock. Drawings In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Fig. 1 is a flowchart of a method for determining power consumption of a chip according to an embodiment of the present invention. Detailed Description The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that th