CN-121995194-A - Clock chip testing method and system

CN121995194ACN 121995194 ACN121995194 ACN 121995194ACN-121995194-A

Abstract

The embodiment of the invention provides a method and a system for testing a clock chip, wherein the method comprises the steps of controlling a power-on time sequence of multiple power domains, powering on the clock chip to be tested, recording a power-on surge current curve and a static power consumption spectrum of each power domain, comprehensively determining the classification of the clock chip to be tested by combining a digital interface, loading initial configuration based on the classification, placing the clock chip to be tested in a high-low temperature box, adjusting test temperature, calculating frequency precision errors at different temperatures, dynamically optimizing load capacitance based on the frequency precision errors to complete chip calibration, testing performance boundaries, signal integrity and short-term reliability of the chip after calibration, and outputting health scores of the clock chip to be tested based on test results.

Inventors

CHEN HUIYUN
XU FANGJING
ZHU JIA
YING BIJIN
WANG SHUAIPENG
HUANG HAICHAO
MA ZHICHENG
ZHAO JINXIONG
YANG YONG

Assignees

杭州海兴电力科技股份有限公司
北京智芯微电子科技有限公司
国网甘肃省电力公司电力科学研究院
国网甘肃省电力公司

Dates

Publication Date: 20260508
Application Date: 20251216

Claims (10)

1. A method of testing a clock chip, the method comprising: Controlling the power-on time sequence of multiple power domains, powering on the clock chip to be measured, recording the power-on surge current curve and static power consumption spectrum of each power domain, comprehensively determining the classification of the clock chip to be measured by combining a digital interface, and loading initial configuration based on the classification; placing a clock chip to be tested in a high-low temperature box, adjusting test temperature, calculating frequency precision errors at different temperatures, and dynamically optimizing a load capacitor based on the frequency precision errors to finish chip calibration; And testing performance boundary, signal integrity and short-term reliability of the chip after calibration, and outputting health scores of the clock chips to be tested based on the test results.
2. The method according to claim 1, wherein the method further comprises: in the chip calibration, the required index required by each temperature point to reach stability is tracked and recorded in real time, and the temperature point with the worst required index is marked as the worst temperature point; the ambient temperature is set to the worst temperature point when performance boundary, signal integrity tests are performed.
3. The method of claim, wherein the step of generating the second data, characterized in that the method further comprises: And based on the health passing rate of the health score, feeding back and adjusting a performance passing threshold of the performance evaluation result.
4. The method of claim 1, wherein said adjusting the test temperature to calculate the frequency accuracy error at different temperatures comprises: The temperature of the high-low temperature box is regulated, the control chip outputs a reference frequency signal, the actual output frequency of the clock chip to be detected is measured through the frequency meter, and the error percentage of the frequency precision error at different temperature points is calculated according to the error percentage between the actual output frequency and the reference frequency signal.
5. The method according to claim 4, wherein the method further comprises: When the error percentage is smaller than a preset threshold value, judging that the temperature point test passes, and storing the corresponding temperature and load capacitance value as one of the optimal configurations of the corresponding clock chip to be tested; When the error percentage is larger than a preset threshold value but does not reach a failure standard threshold value, starting a dynamic load capacitance calibration algorithm; And when the error percentage is larger than the failure standard threshold, repeating iteration until the maximum iteration times are passed, and if the error percentage is still larger than the failure standard threshold, judging that the frequency stability of the clock chip to be detected at the temperature point is unqualified.
6. The method of claim 5, wherein the initiating a dynamic load capacitance calibration algorithm comprises: And combining a pre-stored capacitance-frequency sensitivity model, calculating and setting a new load capacitance value according to an error direction, wherein the error direction is frequency positive bias, increasing the load capacitance, frequency negative bias and reducing the load capacitance.
7. A system for testing a clock chip, the system comprising; The baseline parameter module is used for controlling the power-on time sequence of multiple power domains, powering on the clock chip to be measured, recording the power-on surge current curve and the static power consumption spectrum of each power domain, comprehensively determining the classification of the clock chip to be measured by combining a digital interface, and loading initial configuration based on the classification; The calibration module is used for placing the clock chip to be tested in a high-low temperature box, adjusting the test temperature, calculating frequency precision errors at different temperatures, and dynamically optimizing the load capacitor based on the frequency precision errors to finish chip calibration; and the scoring module is used for testing the performance boundary, the signal integrity and the short-term reliability of the chip after calibration and outputting the health score of the clock chip to be tested based on the test result.
8. The system of claim 7, wherein the system further comprises: The temperature point module is used for tracking and recording a required index required by each temperature point to reach stability in real time in the chip calibration, and marking the temperature point with the worst required index as the worst temperature point, wherein the required index comprises iteration times, a final residual error absolute value or an observed maximum jitter value; and the setting module is used for setting the ambient temperature to be the worst temperature point when performance boundary and signal integrity tests are carried out.
9. An electronic device includes a processor and a memory; the processor is connected with the memory; the memory is used for storing executable program codes; The processor runs a program corresponding to executable program code stored in the memory by reading the executable program code for performing the method according to any one of claims 1-6.
10. A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of any of claims 1-6.

Description

Clock chip testing method and system Technical Field The present invention relates to the field of clock chips, and in particular, to a method and a system for testing a clock chip. Background In the heart of an electronic system, the core of which is a clock chip (such as a crystal oscillator, a phase-locked loop, a clock generator/buffer, etc.), which includes a plurality of data, in mass production testing, it is necessary to perform a comprehensive test on each chip to ensure that it meets all specifications on a data manual. Testing is performed on expensive automated testing equipment, with testing time directly determining testing costs. However, in the prior art, a conventional fixed sequence test is generally used for testing clock chips, and the same time-consuming process is performed on all chips, so that a lot of time is wasted on bad chips. Disclosure of Invention Aiming at the problems existing in the prior art, the embodiment of the invention provides a method and a system for testing a clock chip. The embodiment of the invention provides a method for testing a clock chip, which comprises the following steps: Controlling the power-on time sequence of multiple power domains, powering on the clock chip to be measured, recording the power-on surge current curve and static power consumption spectrum of each power domain, comprehensively determining the classification of the clock chip to be measured by combining a digital interface, and loading initial configuration based on the classification; placing a clock chip to be tested in a high-low temperature box, adjusting test temperature, calculating frequency precision errors at different temperatures, and dynamically optimizing a load capacitor based on the frequency precision errors to finish chip calibration; And testing performance boundary, signal integrity and short-term reliability of the chip after calibration, and outputting health scores of the clock chips to be tested based on the test results. In one embodiment, the method further comprises: in the chip calibration, the required index required by each temperature point to reach stability is tracked and recorded in real time, and the temperature point with the worst required index is marked as the worst temperature point; the ambient temperature is set to the worst temperature point when performance boundary, signal integrity tests are performed. In one embodiment, the method further comprises: And based on the health passing rate of the health score, feeding back and adjusting a performance passing threshold of the performance evaluation result. In one embodiment, the method further comprises: The temperature of the high-low temperature box is regulated, the control chip outputs a reference frequency signal, the actual output frequency of the clock chip to be detected is measured through the frequency meter, and the error percentage of the frequency precision error at different temperature points is calculated according to the error percentage between the actual output frequency and the reference frequency signal. In one embodiment, the method further comprises: When the error percentage is smaller than a preset threshold value, judging that the temperature point test passes, and storing the corresponding temperature and load capacitance value as one of the optimal configurations of the corresponding clock chip to be tested; When the error percentage is larger than a preset threshold value but does not reach a failure standard threshold value, starting a dynamic load capacitance calibration algorithm; And when the error percentage is larger than the failure standard threshold, repeating iteration until the maximum iteration times are passed, and if the error percentage is still larger than the failure standard threshold, judging that the frequency stability of the clock chip to be detected at the temperature point is unqualified. In one embodiment, the method further comprises: And combining a pre-stored capacitance-frequency sensitivity model, calculating and setting a new load capacitance value according to an error direction, wherein the error direction is frequency positive bias, increasing the load capacitance, frequency negative bias and reducing the load capacitance. The embodiment of the invention provides a test system of a clock chip, which comprises: The baseline parameter module is used for controlling the power-on time sequence of multiple power domains, powering on the clock chip to be measured, recording the power-on surge current curve and the static power consumption spectrum of each power domain, comprehensively determining the classification of the clock chip to be measured by combining a digital interface, and loading initial configuration based on the classification; The calibration module is used for placing the clock chip to be tested in a high-low temperature box, adjusting the test temperature, calculating frequency precision errors at different temperatures, a