CN-121995200-A - Compression test system and method based on pin multiplexing

CN121995200ACN 121995200 ACN121995200 ACN 121995200ACN-121995200-A

Abstract

The application discloses a compression test system and method based on pin multiplexing, and relates to the technical field of testability design. The corresponding system comprises a plurality of chip passivation openings, a segment inserting byte unit, a test data register and a compression and decompression unit, wherein the compression and decompression unit is provided with an initial chip passivation opening and at least one standby chip passivation opening, the segment inserting byte unit and the test data register are arranged between the chip passivation opening and the compression and decompression unit and are used for connecting the compression and decompression unit to the standby chip passivation opening arranged in the compression and decompression unit or arranging the compression and decompression unit to the standby chip passivation opening or the initial chip passivation opening of the preset compression and decompression unit under the condition that the initial chip passivation opening corresponding to the compression and decompression unit fails. The application can weaken the influence of the passivation opening performance of the chip on the internal logic test.

Inventors

LI YUJIANG
WANG XINXIN

Assignees

北京清微智能科技股份有限公司

Dates

Publication Date: 20260508
Application Date: 20260108

Claims (10)

1. A compression test system based on pin multiplexing is characterized by comprising a plurality of chip passivation holes, a segment insertion byte unit, a test data register and a compression decompression unit, wherein: The compression and decompression unit is provided with an initial chip passivation opening and at least one standby chip passivation opening; The segment insertion byte unit and the test data register are arranged between the chip passivation aperture and the compression and decompression unit, and are used for connecting the compression and decompression unit to the standby chip passivation aperture configured by the compression and decompression unit in the case that the initial chip passivation aperture corresponding to the compression and decompression unit fails, or The compression and decompression unit is configured to a preset standby chip passivation opening or an initial chip passivation opening of the compression and decompression unit, and the preset compression and decompression unit is configured to a usable chip passivation opening of the compression and decompression unit.
2. The compression test system of claim 1, wherein the die passivation openings comprise a die passivation input opening and a die passivation output opening; The test data register comprises a test data input register and a test data output register; The test data input register is used for matching with the section inserted byte unit to configure the compression and decompression unit initially configured with the failed chip passivation input opening to the corresponding standby chip passivation input opening in the case that the chip passivation input opening fails, or Configuring a compression and decompression unit with initial configuration of the chip passivation input opening with faults to a standby chip passivation input opening or an initial chip passivation input opening of a preset compression and decompression unit, and configuring the preset compression and decompression unit to an available chip passivation input opening of the compression and decompression unit; the test data output register is used for matching with the segment insertion byte unit to configure the compression and decompression unit initially configured with the failed chip passivation output opening to the corresponding standby chip passivation output opening under the condition that the chip passivation output opening fails, or And configuring the compression and decompression unit with the initial configuration of the failed chip passivation output opening to a standby chip passivation output opening or an initial chip passivation output opening of a preset compression and decompression unit, and configuring the preset compression and decompression unit to an available chip passivation output opening of the preset compression and decompression unit.
3. The compression test system of claim 1, wherein the configuration relationship between the compression decompression units and the standby chip passivation openings is determined by the number of logic to be tested and the number of compression decompression units corresponding to the logic to be tested.
4. The compression test system of claim 2, wherein the test data register further comprises a logic under test register for switching in coordination with the segment insertion byte unit and splitting the plurality of logic under test.
5. The compression test system of any one of claims 2 or 4, wherein the test data output register is further configured to output a level value for a chip passivation output aperture, wherein the level value is used to characterize whether the chip passivation output aperture is malfunctioning.
6. The compression test system of claim 5, further comprising a plurality of AND OR gate logic circuits coupled to the test data register and in one-to-one correspondence with a plurality of compression and decompression units for switching a configuration relationship between the compression and decompression units and the chip passivation openings.
7. The compression test system of any one of claims 1-4 and 6, further comprising a test access port controller for multiplexing the same type of compression decompression unit of the plurality of modules with the segment insertion byte unit and the test data register for logic testing and invoking different types of compression decompression units of the plurality of modules for logic testing.
8. A pin multiplexing based compression test method, applied to the pin multiplexing based compression test system of any one of claims 1 to 7, comprising: A segment insertion byte unit and a test data register are arranged between the chip passivation opening and the compression and decompression unit, and the compression and decompression unit is connected to the standby chip passivation opening configured by the compression and decompression unit in the case that the initial chip passivation opening corresponding to the compression and decompression unit fails or The compression and decompression unit is configured to a preset standby chip passivation opening or an initial chip passivation opening of the compression and decompression unit, and the preset compression and decompression unit is configured to a usable chip passivation opening of the compression and decompression unit, wherein the compression and decompression unit is preconfigured with the initial chip passivation opening and at least one standby chip passivation opening.
9. A board comprising the pin multiplexing based compression test system of any one of claims 1 to 7.
10. An electronic device comprising the board card of claim 9.

Description

Compression test system and method based on pin multiplexing Technical Field The application relates to the technical field of integrated circuits, in particular to the technical field of testability design, and in particular relates to a compression test system and method based on pin multiplexing. Background With the slowing of the execution of moore's law, integrated circuits have entered the late moore age, and new technologies, materials and architectures continue to emerge, driving the development of integrated circuits. In this context, the trend in the integrated circuit industry has emphasized multipath innovations in terms of advanced processing, advanced packaging, and architectural innovations. For testability design, the larger the chip design scale is, the larger and longer the scan chain is caused by the huge logic test scan register to be tested due to the limit of the number of chip passivation holes (Passivation Opening, PAD), further affecting the consumption of test time and increasing the chip cost. To solve this problem, the industry breaks down the internal scan chain under the premise of ensuring the external test PAD unchanged, and processes the internal scan chain in parallel through a compression and decompression unit (Compress And Decompress, CODEC) to complete data test control monitoring, and the CODEC unit provides very high compression capability for testability test. Typically, the number relationship between the test ports and the scan chains is 1:200, and each chain has no more than 1000 scan registers controlled under the limitation of test time cost, so for testability design, a pair of CODEC test ports typically completes control monitoring of 20 ten thousand registers. The data flow is aimed at the test transmission process of a certain chip to be tested, namely a test base station, a chip PAD, a CODEC test port, a scanning short chain and a target register, wherein the test base station is independent of a detection tool outside the chip, and for a testability design researcher, in the chip design process under the actual working condition, two orders of magnitude difference still exists between the chip PAD and the CEDEC test port, so that how to compress a test channel between the chip PAD and the target scanning register, and further simplifying the test cost is a technical problem to be solved by a person in the field. This section is intended to provide a background or context to the embodiments of the application that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section. Disclosure of Invention In order to solve at least one of the above problems in the prior art, an embodiment of the present application provides a compression test system and method based on pin multiplexing. Firstly, the embodiment of the application provides a compression test system based on pin multiplexing, which comprises a plurality of chip passivation holes, a segment insertion byte unit, a test data register and a compression decompression unit, wherein: The compression and decompression unit is provided with an initial chip passivation opening and at least one standby chip passivation opening; The segment insertion byte unit and the test data register are arranged between the chip passivation aperture and the compression and decompression unit, and are used for connecting the compression and decompression unit to the standby chip passivation aperture configured by the compression and decompression unit in the case that the initial chip passivation aperture corresponding to the compression and decompression unit fails, or The compression and decompression unit is configured to a preset standby chip passivation opening or an initial chip passivation opening of the compression and decompression unit, and the preset compression and decompression unit is configured to a usable chip passivation opening of the compression and decompression unit. In some embodiments, the chip passivation openings include a chip passivation input opening and a chip passivation output opening; The test data register comprises a test data input register and a test data output register, wherein: The test data input register is used for matching with the section inserted byte unit to configure the compression and decompression unit initially configured with the failed chip passivation input opening to the corresponding standby chip passivation input opening in the case that the chip passivation input opening fails, or Configuring a compression and decompression unit with initial configuration of the chip passivation input opening with faults to a standby chip passivation input opening or an initial chip passivation input opening of a preset compression and decompression unit, and configuring the preset compression and decompression unit to an available chip passivation input opening of the compression and decompression unit; the test data output register is