CN-121995289-A - Test method for online calibration of WAT automatic test capacitance parameters

CN121995289ACN 121995289 ACN121995289 ACN 121995289ACN-121995289-A

Abstract

The invention discloses a test method for carrying out online calibration on WAT automatic test capacitance parameters, which comprises the steps of obtaining machine parasitic parameters, wherein the step of obtaining machine parasitic parameters comprises the steps of providing a calibration capacitance device with the same type as a capacitance device to be tested; and carrying out WAT automatic capacitance test on the calibration capacitance device to obtain a first test capacitance and conductance. And obtaining the parasitic parameters of the machine by converting the first test capacitance and the conductance and the first real capacitance and the resistance. After the parasitic parameters of the machine are obtained, WAT automatic capacitance test is conducted on the capacitance device to be tested to be calibrated so as to obtain a second test capacitance and conductance. And obtaining a second real capacitance and a second real resistance of the capacitance device to be calibrated through conversion of the second test capacitance, the conductance and the machine parasitic parameter. The invention can test the parasitic parameters of the machine on line and can calibrate the capacitance device to be calibrated in time.

Inventors

LIU XIAOMING
FAN MAOCHENG

Assignees

上海华力集成电路制造有限公司

Dates

Publication Date: 20260508
Application Date: 20260120

Claims (8)

1. A test method for performing on-line calibration on WAT automatic test capacitor parameters, comprising: Before WAT automatic capacitance testing is carried out on a capacitance device to be tested, which is to be calibrated and is introduced with a machine parasitic parameter of a WAT automatic test machine, carrying out a step of obtaining the machine parasitic parameter; the step of obtaining the machine parasitic parameter comprises the following steps: providing a calibration capacitor device of the same type as the capacitor device to be tested to be calibrated; the calibration capacitor device is provided with a first real capacitor and a first real resistor which are acquired in advance; Carrying out WAT automatic capacitance test on the calibration capacitance device by adopting the WAT automatic test machine to obtain a first test capacitance and a first test conductance of the calibration capacitance device; Obtaining the parasitic parameter of the machine through conversion of the first test capacitor, the first test conductance, the first real capacitor and the first real resistor; after the machine parasitic parameters are obtained, carrying out WAT automatic capacitance test on the capacitance device to be calibrated so as to obtain a second test capacitance and a second test conductance of the capacitance device to be calibrated; and converting the second test capacitor, the second test conductance and the machine parasitic parameter to obtain a second real capacitor and a second real resistor of the capacitor device to be calibrated.
2. The method for online calibration of WAT automatic test capacitive parameters of claim 1, wherein the calibration capacitive devices are fabricated on corresponding calibration wafers.
3. The method for online calibration of WAT automatic test capacitor parameters according to claim 2, wherein said first real capacitor and said first real resistor are obtained by a semi-automatic test machine with a machine isolation effect and a higher accuracy than said WAT automatic test machine.
4. The method for online calibration of WAT automatic test capacitor parameters of claim 3, wherein said WAT automatic test machine has a wafer table thereon; and after the first real capacitor and the first real resistor are obtained, placing the calibration wafer on the wafer table, and inputting the first real capacitor and the first real resistor corresponding to the calibration capacitor device into a record file of the WAT automatic test machine.
5. The method for online calibration of WAT automatic test capacitance parameters according to claim 1, wherein said machine parasitic parameters comprise machine parasitic capacitance and machine parasitic resistance.
6. The method for online calibration of WAT automatic test capacitor parameters according to claim 1, wherein said scaling formula for machine parasitic parameters comprises: (1); (2); Wherein Cmeas represents the test capacitance measured by the WAT automatic test machine, gmeas represents the test conductance measured by the WAT automatic test machine; Rp represents the true resistance, cp represents the true capacitance; Rs represents the parasitic resistance of the machine, and Cr represents the parasitic capacitance of the machine; ω represents the test angular frequency; When the parasitic parameters of the machine are obtained through conversion of the first test capacitor, the first test conductance, the first real capacitor and the first real resistor, cmeas takes the first test capacitor, gmeas takes the first test conductance, rp takes the first real resistor, cp takes the first real capacitor; When a second real capacitor and a second real resistor of the capacitor device to be calibrated are obtained through conversion of the second test capacitor, the second test conductance and the machine parasitic parameter, cmeas takes the second test capacitor, gmeas takes the second test conductance, rp is the second real resistor, and Cp is the second real capacitor.
7. The method for online calibration of WAT automatic test capacitor parameters according to claim 1, wherein the type of the capacitor to be calibrated comprises an N-type diode capacitor without DNW structure, and the N-type diode capacitor without DNW structure comprises: A P-type well formed on the P-type semiconductor substrate; an n+ electrode region and a p+ electrode region are formed in a selected region of the surface region of the P-type well, with a space between the n+ electrode region and the p+ electrode region.
8. The method for online calibration of WAT automatic test capacitance parameters of claim 4, wherein when a wafer under test with a capacitive device under test is formed begins to perform the WAT automatic capacitance test, further comprising: Judging whether the capacitance device to be tested is the capacitance device to be tested to be calibrated, if not, directly carrying out the WAT automatic capacitance test on the capacitance device to be tested; And if the capacitance device to be tested is judged to be the capacitance device to be calibrated, selecting the calibration wafer with the capacitance device to be calibrated, which has the same type as the capacitance device to be calibrated, from the wafer table, and obtaining the parasitic parameter of the machine.

Description

Test method for online calibration of WAT automatic test capacitance parameters Technical Field The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for performing on-line calibration of WAT automatic test capacitor parameters. Background An Inductance capacitance resistance (CAPACITANCE RESISTANCE, LCR) tester is a measuring instrument for measuring electrical parameters of semiconductor Inductance, resistance and capacitance devices. In mass production wafer level Wafer Acceptance (WAT) testing, LCR testers are most widely used to measure capacitance parameters, and more commonly, capacitance values are oxide layer capacitance (Cox), diode capacitance (Cj), MOM, MIM, etc. The Hi end, i.e., the high voltage end, is usually connected to the body region (Bulk), the Lo end, i.e., the low voltage end, is usually connected to the Gate electrode (Gate) to ensure measurement accuracy and stability, and the simplified measurement circuit diagram is shown in fig. 1, in which the semiconductor device 102 formed on the wafer (wafer) is a diode capacitor, and the wafer is placed on the wafer chuck (chuck) 101, and the wafer chuck is grounded. The diode capacitor has two electrode terminals, both of which are led out through corresponding pads (pads). LCR tester (meter) 103 is connected to one electrode of the diode capacitor through high terminal, i.e., hi terminal, and low terminal, i.e., lo, respectively, and excitation source 104 applies a test signal, and voltmeter 105 and ammeter 106 test voltage and current, respectively. Fig. 2 is an equivalent circuit diagram of fig. 1. It can be seen that the semiconductor device 102 is equivalent to a parallel structure of a capacitor Cp and a resistor Rp. Also shown in fig. 2 is voltage V1, which can be measured by voltmeter 105. However, in the actual batch capacitance test, the N-type capacitance shown in fig. 3 is subject to test data bias when the measuring method shown in fig. 1 is adopted, and is related to the machine and the probe card used. The P-type capacitor of fig. 4 corresponding thereto is normal in test data, and is further described below: As shown in fig. 3, which is a schematic diagram of a measurement structure of a conventional N-type diode capacitor, the semiconductor device 102a is an N-type diode capacitor, and includes a P-type Well (P-Well) 202 formed on a P-type semiconductor substrate (P-sub) 201, an n+ electrode region 203 and a p+ electrode region 204 formed in a surface region of the P-type Well 202, the n+ electrode region 203 being connected to a CML terminal, i.e., a Lo terminal in fig. 1, and the p+ electrode region 204 being connected to a CMH terminal, i.e., a Hi terminal in fig. 1, and the P-type semiconductor substrate 201 being placed on a wafer chuck, i.e., a chuck. As can be seen from fig. 3, in the N-type capacitor, i.e. N-type diode capacitor structure, the p+ electrode region 204 is connected to the P-type well 202 and the P-type semiconductor substrate 201, and the deep N-well (DNW) is not isolated in the middle, so that the signal can directly reach the bottom Chuck through the loop and flow out through the Chuck. It can also be appreciated that the parasitic capacitance of the Chuck loop in the test station is introduced due to insufficient isolation of the N-type capacitance. As shown in fig. 4, which is a schematic diagram of a conventional measurement structure of a P-type diode capacitor, the semiconductor device 102b is a P-type diode capacitor, and includes a P-type Well (P-Well) 202 formed on a P-type semiconductor substrate 201, an N-type Well 206 formed in the P-type Well 202, an n+ electrode region 203 and a p+ electrode region 204 formed in a surface region of the N-type Well 206, the n+ electrode region 203 being connected to a CMH terminal, i.e., a Hi terminal in fig. 1, the p+ electrode region 204 being connected to a CML terminal, i.e., a Lo terminal in fig. 1, and the P-type semiconductor substrate 201 being placed on a wafer chuck, i.e., a chuck. As shown in fig. 4, the P-well 202 and the N-well 206 have capacitances as shown in the virtual coil 207, which have an isolating effect, and do not introduce parasitic capacitances of the Chuck loop in the test equipment. As shown in FIG. 5, which is a capacitance test data graph obtained by measuring the same existing N-type diode capacitance shown in FIG. 3 on different machine stations and probes, it can be seen that when the test machine stations are different, the parasitic parameters corresponding to the machine stations are different, and the sizes of the final tested capacitances are also different. The existing method for solving the difference between the machines comprises the following steps: The capacitance parameters are ensured to be measured on hardware such as a fixed machine, a probe card and the like as much as possible, and different machines with large differences are a