CN-121995292-A - Stability analysis method and system for integrated circuit test equipment

CN121995292ACN 121995292 ACN121995292 ACN 121995292ACN-121995292-A

Abstract

The invention discloses a stability analysis method and a system of integrated circuit test equipment, which relate to the technical field of circuit test and comprise the steps of executing channel replacement scheduling on a test channel formed in the integrated circuit function test process, recording function test response changes before and after the channel replacement scheduling, performing difference arrangement on the function test response changes to generate a channel replacement difference sequence, executing path mapping on a relay connection path corresponding to the test channel according to the channel replacement difference sequence, performing path superposition positioning on a channel difference position in the channel replacement difference sequence according to the relay connection path to generate a relay path difference track, and executing consistency retrieval and path clustering on repeated path difference positions in a history test record to generate a path memory set. According to the invention, the improvement of the abnormal recognition capability of the test channel is realized through the channel replacement scheduling and the functional test response difference arrangement.

Inventors

LI WEIFANXING
ZHANG DELI
SHEN HONGXING
WANG CHAOQUN

Assignees

弘润半导体(苏州)有限公司

Dates

Publication Date: 20260508
Application Date: 20260409

Claims (10)

1. A method for analyzing stability of integrated circuit test equipment is characterized by comprising the steps of, Performing channel replacement scheduling on a test channel formed in the integrated circuit function test process, recording function test response changes before and after the channel replacement scheduling, and performing difference arrangement on the function test response changes to generate a channel replacement difference sequence; performing path mapping on the relay connection path corresponding to the test channel according to the channel replacement difference sequence, and performing path superposition positioning on the channel difference position in the channel replacement difference sequence according to the relay connection path to generate a relay path difference track; expanding corresponding path difference positions along the path difference track of the relay in the history test record, and executing consistency retrieval and path clustering on the path difference positions repeatedly appearing in the history test record to generate a path memory set; And executing stability attribution analysis on the abnormal test channel corresponding to the path difference position through the path memory set, and grading the stability attribution result to generate a stability judging set.
2. The method for analyzing the stability of an integrated circuit test apparatus according to claim 1, wherein said channel replacement schedule is a process of exchanging test connection relations of devices under test between test channels and re-executing functional tests.
3. The method for analyzing stability of integrated circuit testing equipment according to claim 1, wherein said difference sorting means performing position marking and difference aggregation on functional test response changes to form channel difference positions and aggregating into a channel replacement difference sequence.
4. The method for analyzing stability of integrated circuit testing equipment according to claim 1, wherein said positioning of path overlap is performed on channel difference positions in a sequence of channel substitution differences, specifically, In the channel replacement difference sequence, corresponding test channels are determined according to the test channel identifiers corresponding to the channel difference positions; Expanding a relay connection sequence before channel replacement scheduling and a relay connection sequence after channel replacement scheduling along a relay connection path of a test channel; The relay connection sequence before channel replacement scheduling and the relay connection sequence after channel replacement scheduling are correspondingly sorted to form a path comparison sequence; And positioning relay nodes which are continuously consistent in the relay connection paths along the path comparison sequence and marking the relay nodes as path coincident sections, and simultaneously positioning relay nodes which are inconsistent in the relay connection paths and marking the relay nodes as path separation sections.
5. The method for analyzing stability of integrated circuit testing device according to claim 4, wherein generating a relay path difference trace comprises, in particular, Sequentially anchoring the path coincident segment and the path separation segment according to the relay connection sequence after channel replacement scheduling to form a segment bit sequencing sequence; inserting the path separation sections between adjacent path overlapping sections, and arranging the positions according to the section bit ordering sequence to form a difference splicing sequence; Performing end-to-end connection correction on the path coincident segment and the path separation segment in the difference splicing sequence to form a continuous path sequence; And distributing relay nodes corresponding to the marked channel difference positions in the continuous path sequence to generate a relay path difference track.
6. The method for analyzing stability of an integrated circuit test device according to claim 1, wherein said generating a path memory set comprises, in particular, Positioning a path difference position corresponding to the path difference track of the relay in the history test record, and correlating the path difference position with the history test record to form a difference record sequence; Performing consistency search on the difference record sequence, and identifying repeated path difference positions in different test rounds to form a consistency difference sequence; performing path clustering merging on the consistent difference sequences to form path clustering sequences; and (3) gathering clustering results of the path clustering sequences to generate a path memory set.
7. The method for analyzing stability of integrated circuit testing equipment according to claim 6, wherein the history test record is a test execution record formed and stored for each test round in the integrated circuit functional test process; The consistency search is a process of repeating position comparison of path difference positions in a difference record sequence and identifying the same path difference positions.
8. The method for analyzing stability of integrated circuit testing equipment according to claim 1, wherein said stability attribution analysis is to source-locate an abnormal test channel corresponding to a path difference location and to determine an abnormal source channel based on a path memory set.
9. The method for analyzing stability of an integrated circuit test device according to claim 1, wherein the classification includes a stable channel class, a surge channel class, and an abnormal channel class.
10. A stability analysis system for integrated circuit testing equipment is based on the stability analysis method for integrated circuit testing equipment according to any one of claims 1 to 9, and is characterized by comprising, The difference module is used for executing channel replacement scheduling on a test channel formed in the integrated circuit function test process, recording function test response changes before and after the channel replacement scheduling, and performing difference arrangement on the function test response changes to generate a channel replacement difference sequence; The positioning module is used for performing path mapping on the relay connection path corresponding to the test channel according to the channel replacement difference sequence, and performing path superposition positioning on the channel difference position in the channel replacement difference sequence according to the relay connection path to generate a relay path difference track; The retrieval module is used for expanding corresponding path difference positions along the path difference track of the relay in the history test record, and executing consistency retrieval and path clustering on the path difference positions repeatedly appearing in the history test record to generate a path memory set; The dividing module is used for executing stability attribution analysis on the abnormal test channel corresponding to the path difference position through the path memory set, and grading the stability attribution result to generate a stability judging set.

Description

Stability analysis method and system for integrated circuit test equipment Technical Field The invention relates to the technical field of circuit testing, in particular to a method and a system for analyzing stability of integrated circuit testing equipment. Background The integrated circuit testing equipment plays an important role in the development and verification of semiconductors and the mass production process, and the number of testing channels in the automatic testing equipment and the scale of a relay connection network are continuously enlarged along with the continuous improvement of the complexity of the integrated circuit structure. The test channel establishes an electrical connection relationship with the tested device through the relay connection path, and executes operations such as logic function test, time sequence function test, interface communication function test, register read-write function test and the like under the unified test condition. The test channel connection relationship, the relay path structure and the test channel scheduling mode directly influence the stability of the functional test response result, so that the researches of the test channel structure analysis, the relay connection path identification and the functional test response change analysis gradually become important research directions in the field of the stability analysis method of the integrated circuit test equipment. In the technical field of stability analysis of integrated circuit test equipment, the existing method generally relies on statistical analysis of test results or monitoring of relay switch states to evaluate the running states of the test equipment, and the method can reflect the running conditions of a test channel to a certain extent, but when intermittent abnormality occurs in the test channel or local change occurs in a relay connection path, the statistical mode of the test results is difficult to accurately identify the position of an abnormality source, and the internal difference propagation relationship of the relay connection path is also difficult to effectively identify. Disclosure of Invention The present invention has been made in view of the above-described problems occurring in the prior art. Therefore, the invention provides a stability analysis method of integrated circuit test equipment, which solves the problems that the statistical mode of test results is difficult to accurately identify the position of an abnormal source and the internal difference propagation relationship of a relay connecting path is difficult to effectively identify. In order to solve the technical problems, the invention provides the following technical scheme: In a first aspect, the present invention provides a method for analyzing stability of an integrated circuit test device, comprising, Performing channel replacement scheduling on a test channel formed in the integrated circuit function test process, recording function test response changes before and after the channel replacement scheduling, and performing difference arrangement on the function test response changes to generate a channel replacement difference sequence; performing path mapping on the relay connection path corresponding to the test channel according to the channel replacement difference sequence, and performing path superposition positioning on the channel difference position in the channel replacement difference sequence according to the relay connection path to generate a relay path difference track; expanding corresponding path difference positions along the path difference track of the relay in the history test record, and executing consistency retrieval and path clustering on the path difference positions repeatedly appearing in the history test record to generate a path memory set; And executing stability attribution analysis on the abnormal test channel corresponding to the path difference position through the path memory set, and grading the stability attribution result to generate a stability judging set. As a preferable scheme of the stability analysis method of the integrated circuit testing equipment, the channel replacement scheduling refers to a process of exchanging the test connection relation of the tested device among the test channels and re-executing the functional test. As an optimal scheme of the stability analysis method of the integrated circuit testing equipment, the difference arrangement refers to position marking and difference aggregation of functional testing response changes, and channel difference positions are formed and collected into a channel replacement difference sequence. As an optimal scheme of the stability analysis method of the integrated circuit testing equipment, the invention comprises the steps of carrying out path coincidence positioning on the channel difference positions in the channel substitution difference sequence, specifically, In the channel replacement difference seq