CN-121995329-A - C-band radio frequency direct acquisition and data storage system of RFSoC framework

CN121995329ACN 121995329 ACN121995329 ACN 121995329ACN-121995329-A

Abstract

The invention relates to the technical field of radio frequency signal processing, and discloses a RFSoC-framework C-band radio frequency direct acquisition and data storage system, the system comprises a high-speed analog-to-digital conversion module, an on-chip programmable logic processing module, a dual-port block memory module, a DDR (double data Rate) cache module and an upper computer data acquisition module. The C-band radio frequency signals are directly sampled through RFSoC internal ultra-high-speed ADC, after being processed by the programmable logic module, the data are buffered by a two-stage buffer structure formed by BRAM and DDR, and then the data are transmitted to an upper computer through an Ethernet interface to realize real-time receiving, storing and analyzing. The invention realizes direct acquisition of C-band radio frequency signals by adopting RFSoC internal ultra-high speed time staggered architecture ADC, avoids link interference and device noise of the traditional analog down-conversion technology, is matched with a multichannel compensation correction mechanism, greatly improves the acquisition precision of digital signals, and simultaneously reduces external link loss by directly connecting a processing module with an internal Tile-level high-speed interface, and ensures the data continuity and stability under high sampling rate.

Inventors

LI JIALIN
CHEN XURAN
GUO CHENG
HUANG XIAOPING
Xiong Haohuai
ZHAO QING

Assignees

电子科技大学

Dates

Publication Date: 20260508
Application Date: 20260116

Claims (10)

1. A C-band radio frequency direct acquisition and data storage system of RFSoC architecture is characterized by comprising a high-speed analog-to-digital conversion module, an on-chip programmable logic processing module, a dual-port block memory module, a DDR cache module and an upper computer data acquisition module, wherein radio frequency signals are directly sampled through a RFSoC internal super-high-speed ADC, after buffer allocation and data width conversion are completed through the programmable logic module, data are sequentially buffered through BRAM and DDR, and then transmitted to an upper computer through an Ethernet interface, so that real-time receiving and storage of direct acquisition data are realized; The high-speed analog-to-digital conversion module comprises a front end analog input interface, a sample hold circuit, an ADC core, a digital correction module, a digital down conversion module, a clock and synchronization module, wherein the on-chip programmable logic processing module is a PL end of RFSoC and comprises a data access unit, a data format and width conversion unit, a cache scheduling and flow control unit, a multi-path data alignment and synchronization unit and a DMA control and data transmission management unit, the dual-port block memory module comprises a BRAM array unit, a port A access logic, a port B access logic, an address pointer management unit and a data state flag unit, and the DDR cache module comprises a storage control interface, an AXI bus arbitration unit, a DMA burst read-write scheduling unit, a data block organization module, a sequential access control unit and a cache area allocation module.
2. The system of claim 1, wherein the front-end analog input interface of the high-speed analog-to-digital conversion module comprises a voltage reference circuit, an input buffer/driver, a gain and bias adjustment circuit, and a bandwidth limiting filter for conditioning input analog signals and adapting to ADC sampling requirements, and the ADC core employs a time-interleaved ADC architecture with a highest sampling rate up to 5GSPS.
3. The RFSoC architecture C-band radio frequency direct acquisition and data storage system as claimed in claim 1, wherein the data access unit of the on-chip programmable logic processing module directly receives RFSoC high-speed ADCTile original sampling data, the data format and width conversion unit adapts the ADC output format to enable the data width to match BRAM cache and DDR high-speed write link requirements, and the cache scheduling and flow control unit realizes high-speed data writing, peak clipping and distribution to ensure smooth data flow among different cache paths.
4. The system for direct acquisition and data storage of C-band radio frequency of RFSoC architecture according to claim 1, wherein the BRAM array unit of the dual-port block memory module provides on-chip low-delay short-term buffer space for high-speed data stream, the address pointer management unit adopts a ring queue buffer management mode to realize dynamic update of write pointer and read pointer, and the data status flag unit outputs buffer full, buffer empty and threshold alarm flag to ensure data read-write reliability.
5. The system for direct C-band radio frequency acquisition and data storage of RFSoC architecture as claimed in claim 1, wherein the DMA burst read/write scheduling unit of the DDR cache module adaptively sets burst length and write rhythm according to data pressure, the data block organization module divides high-speed continuous sampling data into fixed-specification data blocks for facilitating DDR sequential or segmented storage, the sequential access control unit prevents data coverage and disorder, and the cache area allocation module adopts a multi-cache area or polling cache structure.
6. The system for direct C-band radio frequency acquisition and data storage with RFSoC architecture according to claim 1, wherein the system adopts a BRAM-DDR two-stage buffer structure, wherein BRAM is used for short-term buffering of high-speed data and peak clipping of burst data traffic, DDR is used for continuous buffering of large-capacity and long-time sequence data stream, and data movement between the two-stage buffers is realized by AXIDMA to ensure no data loss under continuous high-speed sampling.
7. The system of claim 6, wherein the BRAM buffer module comprises at least two sets BlockMemoryGeneratorIP of cache memory as on-chip level one caches for multi-channel data, respectively, to achieve data splitting, timing alignment, and burst write management.
8. The C-band radio frequency direct acquisition and data storage system with RFSoC architecture according to claim 1 is characterized in that the system realizes RFSoC high-speed data interaction with an upper computer through an Ethernet data link, a DDR cache module in RFSoC is connected with an Ethernet MAC module through a programmable logic processing module, sampled data is packaged into a network data frame through a UDP data packaging unit, and the network data frame is sent to the upper computer through an Ethernet MAC layer and a PHY interface, so that long-distance, high-bandwidth and continuous data transmission is realized.
9. The RFSoC-structured C-band radio frequency direct acquisition and data storage system according to claim 1, wherein the sampled data of the high-speed analog-to-digital conversion module directly enter the programmable logic processing module through a RFSoC internal Tile-level high-speed interface without passing through an external digital interface chip, the upper computer data acquisition module receives the data through a gigabit or a tera ethernet interface, and stores the data in real time as a binary file, a CSV file or a MAT file, and the upper computer is provided with a frequency domain analysis module for performing real-time spectrum evaluation by using an FFT or a power spectrum estimation algorithm.
10. The C-band radio frequency direct acquisition and data storage system with RFSoC architecture according to claim 1, wherein the upper computer completes the communication from the upper computer to RFSoC through a VITIS tool, and then programs a control command transmitting program with matlab, wherein the control command includes starting signal acquisition, stopping signal acquisition, setting sampling length, selecting ADC channel, starting data transmission, RFSoC end running embedded program, monitoring corresponding port and analyzing and executing control command, configuring ADCTile, data path, AXIDMA and ethernet transmitting module.

Description

C-band radio frequency direct acquisition and data storage system of RFSoC framework Technical Field The invention relates to the technical field of radio frequency signal processing, in particular to a C-band radio frequency direct acquisition and data storage system of RFSoC architecture. Background In an active scaler system, it is necessary to receive radar scaling signals and perform power measurements to provide accurate signal parameters for subsequent signal forwarding. The C-band signal has the characteristic of high frequency and high power, and the accuracy of the reception and measurement directly determines the calibration accuracy. In the prior art, a signal receiving part usually adopts a through analog down-conversion technology, but the technology can generate measurement errors and influence the accuracy of signal acquisition due to the noise introduced by devices of a radio frequency front-end link, and in a signal measuring part, data processing based on FPGA is a common scheme of radar signal processing, but to obtain high-accuracy data, operations which influence the data acquisition, such as extraction, need to be avoided as much as possible, and meanwhile, high-performance FPGA is needed to realize high-efficiency transmission and caching of the data. ZynqUltraScale + RFSoC integrates an ARM processor, a high-speed FPGA and a high-precision radio frequency component on a single-chip SoC platform, so that fusion of a high-performance RF data converter and a radio frequency simulation technology is realized, the high-performance RF data converter comprises 8 RF-ADCs (supporting digital down-conversion DUC) and 8 RF-DACs (supporting digital up-conversion), radio frequency direct acquisition is supported, flexible simulation design capability is realized, the precision is improved, the power consumption is reduced, and a feasible hardware basis is provided for solving the problems of high-precision acquisition and storage of C-band signals. Aiming at the problems that the high-precision radio frequency direct acquisition and signal data storage are difficult to carry out on C-band signals in the prior art, and the signal measurement precision is further influenced, the invention provides a RFSoC-based C-band radio frequency direct acquisition and data storage system so as to realize the high-precision acquisition, stable storage and high-efficiency transmission of the C-band signals Disclosure of Invention In order to overcome the above drawbacks of the prior art, the present invention provides a RFSoC-architecture C-band rf direct acquisition and data storage system, so as to solve the problems set forth in the above background art. The invention provides a RFSoC-architecture C-band radio frequency direct acquisition and data storage system, which comprises a high-speed analog-to-digital conversion module, an on-chip programmable logic processing module, a dual-port block memory module, a DDR (double data rate) cache module and an upper computer data acquisition module, wherein radio frequency signals are directly sampled through a RFSoC internal super-speed ADC (analog-to-digital converter), after cache allocation and data width conversion are completed through the programmable logic module, data are sequentially cached through BRAM and DDR, and then transmitted to an upper computer through an Ethernet interface, so that the real-time receiving and storage of direct acquisition data are realized; The high-speed analog-to-digital conversion module comprises a front end analog input interface, a sample hold circuit, an ADC core, a digital correction module, a digital down conversion module, a clock and synchronization module, wherein the on-chip programmable logic processing module is a PL end of RFSoC and comprises a data access unit, a data format and width conversion unit, a cache scheduling and flow control unit, a multi-path data alignment and synchronization unit and a DMA control and data transmission management unit, the dual-port block memory module comprises a BRAM array unit, a port A access logic, a port B access logic, an address pointer management unit and a data state flag unit, and the DDR cache module comprises a storage control interface, an AXI bus arbitration unit, a DMA burst read-write scheduling unit, a data block organization module, a sequential access control unit and a cache area allocation module. Preferably, the front-end analog input interface of the high-speed analog-to-digital conversion module comprises a voltage reference circuit, an input buffer/driver, a gain and bias adjusting circuit and a bandwidth limiting filter, and is used for conditioning input analog signals and adapting to ADC sampling requirements, and the ADC core adopts a time-interleaved ADC architecture, and the highest sampling rate can reach 5GSPS. Preferably, the data access unit of the on-chip programmable logic processing module directly receives RFSoC high-speed ADCTile original sa