CN-121995570-A - Semiconductor structure and forming method thereof

Abstract

The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises an SO I substrate, a first substrate and a second substrate, wherein the SO I substrate comprises a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate comprises a strip waveguide region and a ridge waveguide region, and a hard mask layer is formed on the surface of the SO I substrate; the strip waveguide is formed in the top silicon layer of the strip waveguide region, and the ridge waveguide is formed in the top silicon layer of the ridge waveguide region. The application provides a semiconductor structure and a forming method thereof, which can optimize the influence of etching load effect, improve the accuracy of etching depth of a ridge waveguide region and a grating region and improve the performance of a device.

Inventors

• LI MINGSHAN
• GAO YING
• WU XUSHENG

Assignees

• 北方集成电路技术创新中心(北京)有限公司

Dates

Publication Date

20260508

Application Date

20241105

Claims (10)

1. 1. A method of forming a semiconductor structure, comprising: providing an SO I substrate, wherein the SO I substrate comprises a bottom silicon layer, an insulating layer and a top silicon layer, and the SO I substrate comprises a strip waveguide area and a ridge waveguide area; forming a hard mask layer on the surface of the SO I substrate; Performing a first etching process, namely etching the hard mask layer and the top silicon layer in the strip waveguide region and the ridge waveguide region, and forming a preparation ridge waveguide in the top silicon layer in the strip waveguide region and the ridge waveguide region; and executing a second etching process, etching the prepared ridge waveguide, converting the prepared ridge waveguide of the strip waveguide region into a strip waveguide and converting the prepared ridge waveguide of the ridge waveguide region into a ridge waveguide.
2. 2. The method of forming a semiconductor structure of claim 1, wherein the preliminary ridge waveguide comprises a main body portion and extension portions extending from a bottom end of the main body portion to both sides, and the second etching process etches the preliminary ridge waveguide in the strip waveguide region while etching a part of the main body portion and all of the extension portions to convert the preliminary ridge waveguide into the strip waveguide.
3. 3. The method of forming a semiconductor structure of claim 2, wherein the SO I substrate further comprises a grating region.
4. 4. The method of forming a semiconductor structure of claim 3, further comprising performing a third etch process to etch the hard mask layer and the top silicon layer of the grating region, forming a grating structure in the top silicon layer of the grating region.
5. 5. The method of claim 4, wherein the third etching process further etches a portion of the rib waveguide region that is preliminary to a body portion of the rib waveguide after the first etching process and before the second etching process.
6. 6. The method of forming a semiconductor structure of claim 4, wherein the third etching process further etches portions of the top silicon layer of the stripe-shaped waveguide region and ridge-shaped waveguide region prior to the first etching process.
7. 7. The method of claim 4, further comprising forming a dielectric layer overlying the SO I substrate on a surface of the SO I substrate, the dielectric layer having a top surface that is level with a top surface of the hard mask layer.
8. 8. A semiconductor structure formed by the method of forming a semiconductor structure as claimed in any one of claims 1 to 7, comprising: The semiconductor device comprises an SO I substrate, a semiconductor substrate and a semiconductor substrate, wherein the SO I substrate comprises a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate comprises a strip waveguide area and a ridge waveguide area, and a hard mask layer is formed on the surface of the SO I substrate; The strip waveguide is formed in the top silicon layer of the strip waveguide region, and the ridge waveguide is formed in the top silicon layer of the ridge waveguide region.
9. 9. The semiconductor structure of claim 8, wherein the SO I substrate further comprises a grating region having a grating structure formed in a top silicon layer of the grating region.
10. 10. The semiconductor structure of claim 8, further comprising a dielectric layer on a surface of said SO I substrate covering said SO I substrate, a top surface of said dielectric layer being level with a top surface of said hard mask layer.

Description

Semiconductor structure and forming method thereof Technical Field The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same. Background The silicon-based photoelectronic passive device integration process can realize the preparation of silicon-based photon passive devices including strip-shaped waveguides, ridge-shaped waveguides, edge couplers, vertical coupling gratings, directional couplers, micro-ring resonators, star-shaped couplers, array waveguide gratings, polarization beam splitters and the like. However, the current silicon-based optoelectronic passive device forming process still has defects. The etching ratio of the bar waveguide in the current silicon-based optoelectronic passive device is about 70% -80%, and the etching ratio of the ridge waveguide and the grating structure is about 10% -20%. Due to the existence of the etching load effect (i load I NG EFFECT, the consumption of local etching gas is larger than the effect of the reduction of etching rate or uneven distribution caused by supply), the etching rate of the ridge waveguide area and the grating structure area is too fast, the accuracy of etching depth control is affected, and the performance of a device is further affected. Therefore, it is necessary to provide a more effective and reliable technical solution, to optimize the influence of the etching load effect, to improve the accuracy of the etching depth of the ridge waveguide region and the grating region, and to improve the device performance. Disclosure of Invention The application provides a semiconductor structure and a forming method thereof, which can optimize the influence of etching load effect, improve the accuracy of etching depth of a ridge waveguide region and a grating region and improve the performance of a device. One aspect of the application provides a method for forming a semiconductor structure, comprising providing an SO I substrate, wherein the SO I substrate comprises a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate comprises a strip waveguide region and a ridge waveguide region, forming a hard mask layer on the surface of the SO I substrate, performing a first etching process to etch the hard mask layer and the top silicon layer in the strip waveguide region and the ridge waveguide region, forming a preparation ridge waveguide in the strip waveguide region and the top silicon layer of the ridge waveguide region, performing a second etching process to etch the preparation ridge waveguide, enabling the preparation ridge waveguide in the strip waveguide region to be converted into the strip waveguide and enabling the preparation ridge waveguide in the ridge waveguide region to be converted into the ridge waveguide. In some embodiments of the present application, the preliminary ridge waveguide includes a main body portion and an extension portion extending from a bottom end of the main body portion to both sides, and the second etching process etches the preliminary ridge waveguide in the strip waveguide region while etching a part of the main body portion and the whole extension portion to convert the preliminary ridge waveguide into the strip waveguide. In some embodiments of the application, the SO I substrate further comprises a grating region. In some embodiments of the present application, the method for forming a semiconductor structure further includes performing a third etching process to etch the hard mask layer and the top silicon layer of the grating region, and forming a grating structure in the top silicon layer of the grating region. In some embodiments of the application, the third etching process is subsequent to the first etching process and prior to the second etching process, the third etching process further etching a portion of the stripe waveguide region that prepares a body portion of a ridge waveguide. In some embodiments of the application, the third etching process further etches portions of the top silicon layer of the stripe-shaped waveguide region and ridge-shaped waveguide region prior to the first etching process. In some embodiments of the present application, the method for forming a semiconductor structure further includes forming a dielectric layer on the surface of the SO I substrate, where the dielectric layer has a top surface that is level with the top surface of the hard mask layer. The application further provides a semiconductor structure formed by the method for forming the semiconductor structure, which comprises an SO I substrate, wherein the SO I substrate comprises a bottom silicon layer, an insulating layer and a top silicon layer, the SO I substrate comprises a strip waveguide region and a ridge waveguide region, a hard mask layer is formed on the surface of the SO I substrate, a strip waveguide is formed in the top silicon layer of the strip waveguide region, and a ridge waveguide is