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CN-121995711-A - Method for generating test pattern set of photoetching process model and related product thereof

CN121995711ACN 121995711 ACN121995711 ACN 121995711ACN-121995711-A

Abstract

The invention relates to a method for generating a test pattern set of a photoetching process model and a related product thereof. The method for generating the test pattern set of the photoetching process model comprises the step of obtaining a standard unit design layout provided by a process design suite. The layers required for testing in the standard cell design layout are divided into a plurality of sub-regions. And positioning key points in each sub-area according to the topological structure of the standard cell design layout. Determining a test pattern according to the key points, and adding the test pattern set. The method for generating the test pattern set of the photoetching process model determines the test pattern by key points, screens out the high-correlation pattern with the photoetching process characterization value, abandons a large number of space overlapping and non-photoetching risk invalid patterns caused by non-differential extraction in the prior art, realizes the accurate compression of the redundancy of the test pattern set, and ensures that the pattern set only keeps a core effective test unit.

Inventors

  • WANG YUJIE
  • GUAN YANG
  • DING MING

Assignees

  • 东方晶源微电子科技(北京)股份有限公司

Dates

Publication Date
20260508
Application Date
20260317

Claims (10)

  1. 1. A method of generating a test pattern set of a lithographic process model, comprising: Obtaining a standard unit design layout provided by a process design suite; Dividing a layer required by testing in the standard cell design layout into a plurality of subareas, wherein a plurality of layout figures are distributed in each subarea; Positioning key points in each subarea according to the topological structure of the standard unit design layout; And determining a test pattern according to the key points, and adding the test pattern set.
  2. 2. The method of generating a test pattern set of a lithographic process model according to claim 1, wherein the step of deriving a test pattern from the keypoints comprises: clustering the key points by using a spatial clustering algorithm based on density to form a key point cluster, and taking the central point of the key point cluster as a cluster key point; Extracting alternative patterns by taking the cluster key points as the center and taking the preset target pattern size as the side length; and screening the test patterns from the alternative patterns.
  3. 3. The method of generating a set of test patterns for a lithographic process model according to claim 2, wherein the step of screening the test patterns from the candidate patterns comprises: and screening alternative patterns among a plurality of layout patterns of which the cluster key points are positioned in the subareas as the test patterns.
  4. 4. A method of generating a test pattern set for a lithographic process model according to claim 3, wherein said step of screening alternative patterns among a plurality of layout patterns in which said cluster key is located within said sub-region as said test pattern comprises: respectively making bounding boxes of each layout figure according to a plurality of layout figures in the subarea; taking the cluster key points as endpoints to respectively take rays to different sides of the bounding box; Taking an included angle between two rays as an included angle of a bounding box of the layout graph; Calculating whether the cluster key points are positioned among a plurality of layout figures in the subarea according to the included angles of the bounding boxes; if yes, taking the alternative pattern as the test pattern.
  5. 5. The method of generating a test pattern set for a lithographic process model according to claim 1, wherein the step of dividing a layer required for testing in the standard cell design layout into a plurality of sub-regions comprises: Acquiring set layout layer parameters; extracting a corresponding layer from the standard cell design layout according to the layout layer parameters; Dividing the layer into a plurality of subareas according to a preset size.
  6. 6. The method of generating a test pattern set of a lithographic process model according to claim 5, wherein said step of locating key points within each of said sub-regions according to the topology of said standard cell design layout, respectively, comprises: Extending the contour line segment of each target graph in the subarea to obtain an intersection point with the contour of other graphs; acquiring the distance between the intersection point and the contour line segment of the target graph; and taking the intersection point with the distance smaller than a preset distance threshold as the key point.
  7. 7. The method of generating a test pattern set for a lithographic process model according to claim 1, wherein the step of determining a test pattern from the keypoints and adding the test pattern set comprises: obtaining a design rule of the photoetching process model; screening out the test patterns in the test pattern set which do not meet the design rule.
  8. 8. A computer program product comprising a computer program, characterized in that the computer program when executed by a processor realizes the steps of the method for generating a test pattern set of a lithographic process model according to any one of claims 1 to 7.
  9. 9. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program when executed by a processor realizes the steps of the method of generating a test pattern set of a lithographic process model according to any of claims 1 to 7.
  10. 10. A computer device comprising a memory, a processor and a computer program stored on the memory, characterized in that the processor executes the computer program to carry out the steps of the method for generating a set of test patterns of a lithographic process model according to any one of claims 1 to 7.

Description

Method for generating test pattern set of photoetching process model and related product thereof Technical Field The invention relates to the field of computational lithography, in particular to a method for generating a test pattern set of a lithography process model and a related product thereof. Background In the integrated circuit manufacturing process, the photolithography process is a key step in determining the chip process node, the degree of integration, and the manufacturing yield. As integrated circuit process nodes continue to advance toward advanced process nodes, imaging accuracy of photolithography and process window control requirements are exponentially improved, and final photolithography imaging quality, process controllability and chip mass production yield are directly determined by calibration accuracy of photolithography process models. The test pattern is a core carrier for calibrating, calibrating and verifying a photoetching process model, and optimizing photoetching model parameters by comparing a simulated predicted critical dimension with an actual manufacturing measured dimension is a key for improving photoetching process controllability and chip manufacturing yield. The current mainstream lithographic test pattern generation schemes in the industry are mainly divided into three categories. The first type is parameterized synthesized array patterns defined based on few geometric parameters, such as line patterns with different line widths and pitches, circular array patterns, square array patterns, stepped patterns and the like, the patterns can realize the height controllability of the patterns through parameter adjustment, the core indexes such as the shape, the outline, the filling rate and the like of the patterns in the photoetching process can be evaluated in a targeted manner, and the parameterized synthesized array patterns are basic test patterns widely applied to mature process nodes. The second category is a layout pattern extracted based on a real chip design layout, and the scheme screens representative patterns from the real chip design as test patterns, is highly close to the real design, and can accurately reflect complex topological features of the chip layout in the prior process. The third category is test pattern design schemes based on human experience, relying on experience accumulated by process developers to design, or test pattern migration from mature process nodes to new development process nodes. However, as the process nodes of the integrated circuit are continuously reduced, the complexity of the manufacturing process is greatly improved, and the technical defects that the prior art scheme is difficult to adapt to the development requirement of the advanced process are gradually exposed. The existing technical scheme can not solve the problems of high redundancy of the test pattern set and large duty ratio of invalid patterns. Resulting in a prolonged test period and wasted test resources. Disclosure of Invention It is an object of the present invention to overcome at least one of the drawbacks of the prior art and to provide a method for generating a test pattern set of a lithographic process model and related products. It is a further object of the present invention to compress the redundancy of a pattern set to shorten the test period and reduce the consumption of test resources. The invention provides a method for generating a test pattern set of a photoetching process model, which comprises the steps of obtaining a standard unit design layout provided by a process design suite, dividing a layer required by testing in the standard unit design layout into a plurality of subareas, positioning key points in each subarea according to the topological structure of the standard unit design layout, determining test patterns according to the key points, and adding the test pattern set. The method comprises the steps of selecting a target pattern size, selecting a test pattern from the target pattern sizes, selecting a cluster of the target pattern size, selecting a test pattern from the test pattern sizes, selecting a cluster of the target pattern size, and selecting the target pattern size. Optionally, the step of screening the test pattern from the candidate patterns includes screening the candidate patterns between the plurality of patterns with the cluster keypoints located within the sub-region as the test pattern. The method comprises the steps of selecting a plurality of patterns in a subarea, selecting alternative patterns among the patterns in the subarea, selecting the alternative patterns among the patterns in the subarea as test patterns, respectively making bounding boxes of each pattern according to the patterns in the subarea, respectively taking the cluster key points as end points to respectively radiating to different sides of the bounding boxes, taking included angles between two radiating lines as bounding box included angles of lay