CN-121995724-A - Synchronous time-to-charge converter

Abstract

The application relates to a synchronous time-to-charge converter. The time-to-charge converter includes a phase detector for receiving a first clock and a second clock and outputting a phase error signal indicative of a time difference between the second clock and the first clock, a current source for generating a tail current, a current steering network for steering the tail current to a first node or a second node according to the phase error signal, a synchronous clock generator for receiving the first clock and generating a third clock synchronous with the first clock but having an independently determined duty cycle, an integrating capacitor having a top plate connected to the second node and a bottom plate driven by an inverted signal of the third clock, a switch disposed between and controlled by the third node, and a load capacitor connected to the third node.

Inventors

• LIN JIALIANG

Assignees

• 瑞昱半导体股份有限公司

Dates

Publication Date

20260508

Application Date

20250514

Priority Date

20241108

Claims (9)

1. 1.A time-to-charge converter, comprising: a phase detector for receiving a first clock and a second clock and outputting a phase error signal indicative of a time difference between the second clock and the first clock; a current source for generating a tail current; A current steering network for steering the tail current to a first node or a second node according to the phase error signal; A synchronous clock generator for receiving the first clock and generating a third clock synchronous with the first clock and having an independent determined working period; an integrating capacitor, a top plate of which is connected to the second node, and a bottom plate of which is driven by an inverse signal of the third clock; a switch arranged between a third node and the second node and controlled by the third clock, and And a load capacitor connected to the third node.
2. 2. The time to charge converter of claim 1, wherein the first clock is a reference clock having a settling period timing.
3. 3. The time to charge converter of claim 2, wherein the first clock is generated by a crystal oscillator.
4. 4. The time to charge converter of claim 1, wherein the phase error signal generates a rising edge at a rising edge of the second clock and a falling edge at a rising edge of the first clock.
5. 5. The time-to-charge converter of claim 4, wherein the current steering network comprises: A second switch controlled by the phase error signal and interposed between a junction node and the second node, and A first switch controlled by an inverse of the phase error signal and interposed between the junction node and the first node, wherein the junction node is connected to the current source.
6. 6. The time-to-charge converter of claim 1, further comprising: a low impedance active load is connected to the first node and includes a metal oxide semiconductor transistor having a source connected to the first node.
7. 7. The time-to-charge converter of claim 1, further comprising: An offset charge transfer circuit, comprising: A metal oxide semiconductor field effect transistor configured as a common gate amplifier, a drain of the metal oxide semiconductor field effect transistor being connected to the third node, a source of the metal oxide semiconductor field effect transistor being connected to a source node through a source switch controlled by the third clock, and a gate of the metal oxide semiconductor field effect transistor being controlled by a reference voltage; A source capacitor interposed between a power supply node and the source node, and And a reset switch controlled by the inverted signal of the third clock and interposed between the power supply node and the source node.
8. 8. The time to charge converter of claim 7, further comprising: A reference voltage generator comprising a current source and a mosfet, wherein the mosfet is arranged in a topology connected in the form of a diode, a drain of the mosfet is connected to a gate of the mosfet and to the current source, a source of the mosfet is connected to the power supply node through a resistor, and the reference voltage is taken from the gate of the mosfet.
9. 9. The time-to-charge converter of claim 1, wherein the synchronous clock generator comprises: a delay circuit for receiving the third clock and outputting a delayed clock, and A data trigger for outputting the third clock according to the first clock and the delay clock, Wherein the first clock performs a trigger function and the delay clock performs a reset function.

Description

Synchronous time-to-charge converter Technical Field The present disclosure relates to time-to-charge converters, and in particular to time-to-charge converters synchronized with a reference clock. Background Those skilled in the art will understand and appreciate terms and basic concepts related to microelectronics, such as "voltage," "current," "signal," "logic signal," "clock," "phase," "edge (clock," "duty cycle," "capacitance," "transistor," "node," "ground node," "power supply node," "inverter," "switch," "common gate amplifier," "load," "flip-flop," "noise," and "impedance," as used in this disclosure. The use of the above terms and concepts in the present disclosure will be readily apparent to those skilled in the art and therefore do not require further detailed description. A Metal-Oxide-semiconductor field effect transistor (MOSFET), hereinafter referred to as "MOS transistor" or "MOST", is an active device comprising a source terminal, a gate terminal and a drain terminal, and is operable as an amplifier or a switch. MOST includes NMOS (n-channel) and PMOS (p-channel) transistors. When the voltage between the gate and the source is lower than a certain threshold voltage, the MOST remains off and exhibits an open-circuit-like characteristic. When the voltage between the gate and the source exceeds the threshold voltage, the MOST enters an on state, in which case the MOST operates in the "saturation region" and can effectively operate as an amplifier if the voltage between the gate and the drain is below the threshold voltage. Conversely, when the voltage between the gate and the drain exceeds the threshold voltage, the MOST operates in the "linear region" and acts as a switch. Those skilled in the art will recognize the notation of MOST, whether PMOS or NMOS transistors, and will recognize the "source", "gate" and "drain" terminals of MOST. For brevity, in this disclosure, the "source end" of MOST is simply referred to as the "source", the "gate end" is simply referred to as the "gate", and the "drain end" is simply referred to as the "drain". Those skilled in the art will readily understand the connection of resistors, capacitors, MOS transistors, inverters, switches and other components in the circuit schematic. Therefore, a detailed description of the interconnections between these elements is not necessary. A signal is a signal with a variable level or current, carries specific information, and can vary with time. The potential of a signal at a certain moment represents the signal state at that moment. If the signal is a voltage (current), it is referred to as a "voltage signal" ("current signal"). In the present disclosure, since "voltage signal" occurs more often than "current signal", for brevity, "signal" refers to "voltage signal" unless specifically indicated as "current signal". The logic signal contains two distinct states, low (0) and high (1). "Q is high (1)" means that Q is in a high (1) state, and "Q is low (0)" means that Q is in a low (0) state. Logic signals may be used to enable or disable a function, the state in which the function is enabled being referred to as the "on state" in this disclosure. When the logic signal transitions from a low (0) state to a high (1) state, or from a high (1) state to a low (0) state, corresponding to the occurrence of a rising edge or a falling edge, respectively. Thus, a pulse of a logic signal may be defined to start at a rising edge and end at a subsequent falling edge. The clock is a logic signal that periodically toggles between 0 and 1. The duty cycle of a clock is the percentage of the time the clock remains in the 1 state over the entire period. The time of a clock refers to the point in time at which the rising edge of the clock occurs. The time difference between the first clock and the second clock refers to the amount of separation between the point in time when the rising edge of the first clock occurs and the point in time when the rising edge of the second clock occurs. In this disclosure, "time" and "timing" have the same meaning in the context of clock related, and are used interchangeably, both referring to the point in time at which a rising edge occurs. In many applications, a time-to-charge converter (TCC) is required, which is used to detect the time difference between the first clock and the second clock and convert the time difference into charged particles (hereinafter simply referred to as charges) proportional thereto. As shown in fig. 1, TCC 100 includes a Phase Detector (PD) 110 for detecting a time difference between a first clock CK1 and a second clock CK2 and outputting a phase error signal, which is commonly represented by two logic signals UP and DN, to characterize the time difference, and a Charge Pump (CP) 120 for converting the phase error signal into a charge that is transferred to an output node 101, the output node 101 terminating in a load 130, the load 130 including a shunt capacitor 131 in parallel w