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CN-121995823-A - Multichannel AD9361 controller based on ZYNQ and control method

CN121995823ACN 121995823 ACN121995823 ACN 121995823ACN-121995823-A

Abstract

The invention relates to a multichannel AD9361 controller based on ZYNQ and a control method thereof, and relates to the technical field of digital signal processing. The ARM processing system comprises an ARM processing system and a programmable logic system, wherein a controller module and a signal processing algorithm module are arranged in the programmable logic system, the controller module comprises an AD9361 controller 1 arranged in the ARM processing system, an AD9361 controller 2, an arbiter, an AXI controller and a data distributor which are arranged in the programmable logic system, the ARM processing system further comprises independent SPI interfaces and independent GPIO interfaces which are in one-to-one correspondence with all AD9361 chips, the AD9361 controller 1 and the AD9361 controller 2 apply data transmission control rights to the arbiter according to control requirements, all the independent SPI interfaces and the independent GPIO interfaces are respectively connected with SPI pins and GPIO pins of corresponding AD9361 chips, and the ARM processing system and the programmable logic system are interconnected through an AXI bus. The invention can be externally connected with a plurality of AD9361 chips and supports multichannel parallel control.

Inventors

  • YANG ZHIWEN
  • TANG WEI
  • LIANG TAO

Assignees

  • 湖南智领通信科技有限公司

Dates

Publication Date
20260508
Application Date
20260120

Claims (9)

  1. 1. A multichannel AD9361 controller based on ZYNQ is characterized by comprising an ARM processing system and a programmable logic system, wherein a controller module and a signal processing algorithm module are arranged in the programmable logic system; the controller module comprises an AD9361 controller 1 arranged in an ARM processing system, an AD9361 controller 2, an arbiter, an AXI controller and a data distributor which are arranged in a programmable logic system, and also comprises independent SPI interfaces and independent GPIO interfaces which are in one-to-one correspondence with all AD9361 chips; the AD9361 controller 1 and the AD9361 controller 2 apply data transmission control rights to the arbiter according to control requirements; The data distributor receives the address and the configuration information of the AD9361 controller 2 or the AD9361 controller 1 and distributes the address and the configuration information to the corresponding independent SPI interface and independent GPIO interface according to the target address; Each independent SPI interface and each independent GPIO interface are respectively connected with the SPI pin and the GPIO pin of the corresponding AD9361 chip; the signal processing algorithm module is connected with each AD9361 chip through a data interface, and the ARM processing system is interconnected with the programmable logic system through an AXI bus.
  2. 2. The ZYNQ-based multichannel AD9361 controller of claim 1, wherein the signal processing algorithm module comprises a scrambling sub-module, an interleaving sub-module, a convolution sub-module, a modulation sub-module, and an IFFT sub-module; The scrambling submodule, the interleaving submodule, the convolution submodule, the modulation submodule and the IFFT submodule are sequentially cascaded and interact data through an internal bus.
  3. 3. The ZYNQ-based multichannel AD9361 controller of claim 1, wherein the independent SPI interfaces comprise clock pins, data input pins, and data output pins, each connected in one-to-one correspondence with an SPI clock pin, an SPI data input pin, and an SPI data output pin of a corresponding AD9361 chip.
  4. 4. The ZYNQ-based multichannel AD9361 controller of claim 1, wherein the independent GPIO interface comprises a reset pin and an enable pin, which are connected in one-to-one correspondence to a reset control pin and an operational enable pin of a corresponding AD9361 chip, respectively.
  5. 5. The ZYNQ-based multichannel AD9361 controller according to any one of claims 1 to 4, wherein the data interface is an LVDS high-speed differential interface for transmitting radio frequency acquisition data and transmission data of the AD9361 chip.
  6. 6. The ZYNQ-based multichannel AD9361 controller of any one of claims 1-4 wherein the AXI controller interfaces directly with an on-chip AXI interconnect matrix of an ARM processing system using AXI4-Lite protocol.
  7. 7. A multichannel AD9361 chip control method based on ZYNQ, the method comprising: In the initial stage of system power-on, an AD9361 controller 2 in a programmable logic system sends initialization configuration signals to corresponding AD9361 chips in parallel through independent SPI interfaces and independent GPIO interfaces; After the initialization is completed, the controller module enters a mode selection state, and the arbiter detects the PL control enabling signal and the PS control enabling signal in real time; If the PS control enabling signal is detected to be valid, the arbiter distributes SPI bus control rights to the AXI controller, and the ARM processing system transmits read-write control signals to the AD9361 chip through the AXI bus, the AXI controller, the data distributor, each independent SPI interface and each independent GPIO interface; If the PL control enable signal is detected to be valid, the arbiter distributes SPI bus control rights to the AD9361 controller 2, and the programmable logic system transmits read-write control signals to the AD9361 chip through the AD9361 controller 2, the data distributor, each independent SPI interface and each independent GPIO interface.
  8. 8. The ZYNQ-based multichannel AD9361 chip control method of claim 7, further comprising: After the ARM processing system or the programmable logic system finishes the transmission of the read-write control signal, the arbiter releases SPI bus control right; the controller module returns to the mode selection state after maintaining the preset idle time, and waits for the next triggering of the enabling signal.
  9. 9. The ZYNQ-based multichannel AD9361 chip control method as claimed in claim 7, wherein the PL control enable signal and the PS control enable signal are mutually exclusive signals and are active at high level, and when the arbiter detects that both enable signals are active at the same time, SPI bus control rights are allocated to the AD9361 controller 2 by default.

Description

Multichannel AD9361 controller based on ZYNQ and control method Technical Field The invention relates to the technical field of digital signal processing, in particular to a multichannel AD9361 controller based on ZYNQ and a control method. Background The AD9361 chip is used as a high-performance highly-integrated agile transceiver, integrates a complete set of core modules such as filtering, amplifying, gain control, frequency synthesizer and the like, can effectively reduce the volume, power consumption and cost of the radio frequency transceiver module, and the performance can meet the requirements of all current communication modes, so that the architecture formed by the AD9361 chip and the ZYNQ chip is widely applied to the fields of software radio, wireless communication and the like. However, the configuration mode of the AD9361 chip directly affects the operation efficiency and the adaptation capability of the whole system. At present, three main schemes mainly exist for configuration of ZYNQ and AD9361 chips, wherein the configuration mode is realized by simulating SPI interfaces on the PL side, the real-time performance of the configuration is extremely high, PS resources are not occupied, initialization can be completed rapidly, but the development and debugging process is complex, the register configuration sequence is strictly required, parameter modification is required to recompile FPGA engineering, flexibility is extremely poor, ADI official No-OS driven C language codes can be multiplexed by adopting the PS side direct configuration mode, the development difficulty is low, the parameter modification is flexible and the portability is strong, but ARM cores of PS are required to process multitask scheduling, the real-time performance of the configuration is poor, the situation that time scale requirements such as a baseband algorithm are strict is difficult to adapt, resource conflict is easily caused by depending on the peripheral interfaces, the PS side drives PL configuration mode through an AXI protocol, the flexibility and the hardware suitability are considered, the configuration and the data path are separated, the common layout is adapted, the instruction transmission is required to pass through PS software processing, AXI bus transmission, SPI conversion links and the like, the additional link delay exists, the configuration speed is not required to be increased, and the development process is required to be carried out by a pure PL logic interface, and the development end is required to be written by a developer, and the PL logic interface is high. It can be seen that the three schemes have inherent limitations, which cannot support parallel control of multiple AD9361 chips, cannot meet the requirements of a multi-channel radio frequency transceiving scene, cannot realize cooperative control and flexible switching of PS and PL on the AD9361 chips, and cannot simultaneously consider the high-speed initialization advantage of PL and the flexible parameter adjustment capability of PS. Disclosure of Invention Accordingly, in order to solve the above-mentioned problems, it is necessary to provide a multichannel AD9361 controller and a control method based on ZYNQ, which can support multichannel parallel control and achieve both high-speed initialization and flexible adjustment. A ZYNQ-based multichannel AD9361 controller comprising: ARM processing system and programmable logic system, the programmable logic system includes controller module and signal processing algorithm module The controller module comprises an AD9361 controller 2, an arbiter, an AXI controller, a data distributor, an independent SPI interface and an independent GPIO interface which are in one-to-one correspondence with all AD9361 chips, and an AD9361 controller 1 arranged in an ARM processing system; the AD9361 controller 1 and the AD9361 controller 2 apply data transmission control rights to the arbiter according to control requirements; The data distributor receives the address and the configuration information of the AD9361 controller 2 or the AD9361 controller 1 and distributes the address and the configuration information to the corresponding independent SPI interface and independent GPIO interface according to the target address; Each independent SPI interface and each independent GPIO interface are respectively connected with the SPI pin and the GPIO pin of the corresponding AD9361 chip; the signal processing algorithm module is connected with each AD9361 chip through a data interface, and the ARM processing system is interconnected with the programmable logic system through an AXI bus. On the other hand, a multichannel AD9361 chip control method based on ZYNQ is also provided, and the method comprises the following steps: In the initial stage of system power-on, an AD9361 controller 2 in a programmable logic system sends initialization configuration signals to corresponding AD9361 chips in parallel through ind